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Multi-layer Interconnect Technology
To meet the challenge of reducing total power consumption in IC chips, minimization of standby current leakage from transistors must be accompanied by a reduction in the power consumption of interconnects between transistors. The shrinking geometries and enhanced functionality of advanced SOCs have led to an increase in the number and length of interconnect lines, which tends to increase the ratio of the interconnect load capacitance to the chip's total load capacitance. Reducing parasitic capacitance in interconnects is crucial to reducing total power consumption.
In its 55 nm process, NEC Electronics has succeeded in reducing power consumption while also achieving higher speeds by simplifying the interconnect structure and introducing a porous low-k dielectric to suppress parasitic capacitance.
The principal features of the 55 nm interconnect technology are as follows.
Dual damascene (DD) structure for lower interconnect delay
A simplified dual damascene structure was adopted, in which line trenches and via holes are formed simultaneously. This reduces interconnect delay and enables higher operating speeds.
Porous low-k dielectric film to suppress parasitic capacitance
NEC Electronics was an early advocate of the introduction of low-k dielectric films to reduce parasitic capacitance in interconnects. A rigid low-k dielectric film was successfully adopted for the 90 nm node, and for the 55 nm node further improvements have been obtained through the use of a porous low-k dielectric film with sub-nanometer pores.
Higher performance through thinner barrier film
The RC product (a measure of signal propagation performance) was improved by adopting a structure that halved the thickness of the high-resistance barrier film.
Low thermal load process prevents defects due to thermal aggregation
By switching from copper to a copper alloy for the interconnect material, NEC Electronics was able to suppress defects due to thermal aggregation in fine-pitched via interconnects.
