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55 nm process features
At NEC Electronics, the 55 nm device process provides the foundation for system-on-chip solutions that meet the requirements of a wide range of applications, from mobile phone handsets to network equipment, by delivering high speed and low power at the same time.
Low power consumption
The outstanding feature of 55 nm devices is that they deliver low power consumption without sacrificing high operating speeds. By combining high-k films in transistor gates and porous low-k films in interconnect insulation, NEC Electronics has achieved the ultimate in low power consumption.
For details, see the following pages.
Ultra-fine geometries through immersion lithography
NEC Electronics was the first IC manufacturer in Japan to adopt immersion lithography, using it to achieve precise control over the ultra-fine patterns in the 55 nm process. Immersion lithography fills the gap between the scanner and the wafer with water, allowing the numerical aperture (NA) of the lens to be increased well beyond the theoretical limit (1.0) of an air gap, and thereby increasing the resolution of the scanner.
Large-scale embedded memory
Large-scale integrated memory is a critical component of the one-chip systems that power an increasing number of applications. NEC Electronics pioneered embedded DRAM (eDRAM), and is committed to the development of an eDRAM process to match each advance in the standard CMOS process. Of course, this includes the state-of-the-art 55 nm CMOS process. For details, see the page below.
In SRAM transistor cells with narrow channel widths, there is a tendency for Vth to decrease and current leakage to increase at locations where channel widths are narrowest, a phenomenon called the "inverse narrow-channel effect". Normally this makes additional ion implantation steps necessary, separate from the logic steps. But in NEC Electronics' 55 nm process, a thin hafnium-silicate (HfSiOx) film in the gate dielectric works to control Vth, making it possible to fabricate the SRAM section and the logic section in the same ion implantation step. The result is a dramatic reduction in the number of process steps.
In addition, the introduction of immersion lithography enables the fabrication of SRAM with a cell size of only 0.446μm2.
