Beginning of this page
Jump to main content

Please note that JavaScript and style sheet are used in this website,
Due to unadaptability of the style sheet with the browser used in your computer, pages may not look as original.
Even in such a case, however, the contents can be used safely.

Products > Packages > Trends in package development > SMAFTI >

SMAFTI® Technology


Proprietary attachment process with 50µm bump pitch and 100 Gbps data transmission


The introduction of a silicon-to-silicon attachment process has enabled chip-to-chip connection with a 50µm bump pitch, which is about 1/4th of the conventional pitch size for connection to printed wiring boards. Consequently, the number of pins interconnecting logic and memory chips can be increased, enabling high-speed data transmission of 100 Gbps, which is over 10 times faster than conventional transmission rates.

 


Figure
SMAFTI Architecture Overview


Number of signal connections between memory and logic chips (bus width)

Conventional

Figure
32-bit memory bus width
 

SMAFTI

Figure
Bus width increases to over 512 bits


-
©NEC Jisso and Production Technologies Research Laboratories 2006
Click on the arrow keys to view the 3D image from different angles. Actual specifications and dimensions vary from the displayed image.


SMAFTI is a registered trade mark in Japan, Germany, Korea, and Taiwan.