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Products > Packages > Trends in package development > SMAFTI >

SMAFTI® Process


Proprietary leading-edge wafer assembly technology

A feature of the SMAFTI process is that all processes are performed at the wafer level. A memory chip is first mounted onto a silicon wafer which has been wired based on superconnect technology. Next, the chip and wiring layer are encapsulated by resin, the silicon wafer is removed, and a logic chip is mounted onto the back side.
Solder balls were also formed on the back side to form a BGA (Ball Grid Array) which acts line external pins.
This proprietary SMAFTI wafer assembly technology contributes to efficient production because it can be used in production infrastructures of existing packages, such as wafer-level CSPs, and because the package can be made by only connecting the chips and the superconnect traces, without using a substrate as in conventional packaging.



SMAFTI process


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©NEC Jisso and Production Technologies Research Laboratories 2006


Features of SMAFTI

  • Small package size on which you can mount logic chip and 1-Gbit-class memory
  • High-speed signal transmission
  • High-definition image processing
  • Low power consumption
  • Low-impedance power lines
  • Broad memory bus width
  • All processes at wafer level
  • Low cost




SMAFTI is a registered trade mark in Japan, Germany, Korea, and Taiwan.