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Products > ASIC > PFESiP >

EP-1 Series Product Specifications


The EP-1 Series product specifications are described below.


EP-1 Series 16-bit external bus block diagram
EP-1 Series 16-bit external bus block diagram

CPU for the EP-1 Series (V850E2 core)

The microcontroller mounted onto the EP-1 Series is specially designed, based on the NEC Electronics MCU V850E2/ME3 microcontroller that has a proven track record.


  • Maximizes the rich resources of the V850 microcontrollers
    • Development using universal methods is taken into consideration by employing V850 microcontroller development tools.
  • On-chip cache function and internal instruction RAM
    • Both instruction cache and data cache are incorporated, and throughput enhancement is achieved.
    • Instruction RAM (192 KB) that fetches at high speed and with the same clock as the CPU is incorporated.
    • 32 KB work RAM is provided.
  • On-chip remap function of the chip select function
    • Mixed incorporation of the data cache enable area and disable area in a single memory has been made possible.
  • On-chip USB 2.0 FS host function
  • Adoption of the PLL synthesizer (SSCG) for handling EMI

Detailed specifications of the EP-1 Series-dedicated microcontrollers


Item Major Specifications
CPU core NBA85E2S 200 MHz operation, 7-stage pipeline
On-chip debug function N-Wire I/F on-chip debug function
Number of traces: 8
On-chip cache Instruction cache: 8 KB
Data cache: 8 KB
Instruction RAM 192 KB (200 MHz × 1-clock operation)
Data RAM 32 KB (200 MHz × 1-clock operation)
Work RAM 32 KB (100 MHz × 2-clock operation)
Minimum instruction execution time 5.00 ns (during 200 MHz operation)
DMA controller 4 channels
External memory access SRAM/PageROM/SDRAM, on-chip chip select remap function
Interrupt NMI × 1, maskable × 88 (internal: 56, external: 24, within SP: 8)
Standby function IDLE/HALT
I/O ports 121 maximum (depending on the specifications of SiP development)
Peripheral functions Timer C × 4, Timer D × 6, Timer ENC × 2, PWM × 2,
UART × 4, CSI (SPI) × 2, A/D converter
USB host function USB 2.0 FS × 2 channels, 2-channel Root-Hub function
USB function USB 2.0 FS × 1 channel, number of end points: 4

  Remark

  • Some of the functions may not be usable, depending on the external bus width and the selected package.
    Refer to the manual of each product.


Characteristics of the SiP technology

SiP
  1. Minimized wire delay through direct bonding
  2. Optimized I/O drive capacity. Small waveform distortion and reduced EMI radiation.
  3. Verified signal integrity of the connections between the microcontroller and gate array, and power integrity. No analysis time and cost required.


User logic

  • The user logic is realized by using a 0.35 µm gate array (practically EA-9HD created with the same technology) that has an established reputation through its track record of numerous adoptions.
    • A short TAT can be achieved.
  • Countermeasures, such as using a PLL synthesizer (SSCG) and capacity embedding which are effective for handling EMI noise can be performed.

Power supply voltage

  • Internal: 1.5 V, I/O: 3.3 V