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Products > ASIC > PFESiP >

EP-1 Series Lineup


The EP-1 Series provides a lineup of six products, each varying depending on the selected external bus width as well as the size of the gate array to be mounted. A 32-bit or 16-bit external bus can be selected for the CPU (standard support product).
Customers who wish to change the ASIC that is to be equipped with devices, such as a package or user logic, can receive customized*1 support.

Note(*)

  1. We develop packages meeting customer requests.
    Separate development costs will, however, arise.
    Master development costs will arise when creating a user logic using a cell-based IC.

External Bus 16-bit

*Click a package name to view the package drawing.

Master
(Standard) 		External Bus Number of Usable Gate Package (BGA) A/D DMA
channel
464-pin
(25 x 30mm, 1.0mm pitch) 		417-pin
(22 x 22 mm, 0.8 mm pitch) 		433-pin
(17 x 17 mm, 0.65 mm pitch)
MC-10501 16-bit 80 K - - 2
MC-10502 160 K -
MC-10503 240 K - -

Remarks   : Available, : Planning


  1. User signal count: 80
  2. Power supply voltage
    • PFESiP microcontroller: Internal 1.5V
    • Gate Array and Embedded Array: Internal 3.3V
    • I/O (common): 3.3V
  3. The CPU operation frequency is 100 MHz (maximum) with packages less than 22 × 22 mm in size.

External Bus 32-bit

Master
(Standard) 		External Bus Number of Usable Gate Package (BGA) A/D DMA
channel
572-pin
(25 x 30mm, 1.0mm pitch) 		550-pin
(25 x 30mm, 1.0mm pitch)
MC-10505 32-bit 80 K - 10 bit x 8 channels
500kHz 		4
MC-10506 160 K
MC-10507 240 K

Remarks   : Available, : Planning


  1. User signal count: 572-pin: 120, 550-pin: 80
  2. Power supply voltage
    • PFESiP microcontroller: Internal 1.5V
    • Gate Array and Embedded Array: Internal 3.3V
    • I/O (common): 3.3V