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EP-1 Series Development Environment
A well-equipped development environment plays an important role for the employment of an ASIC, such as the PFESiP.
Especially for an SiP, such as the EP-1 Series, a design environment for the user logic, a software design environment for the mounted CPU, and an environment enabling an evaluation by combining the user logic and CPU are required.
The development of a development environment can be significantly facilitated if a V850 microcontroller and gate array have been developed in the past, since their development environments can be used for the EP-1 Series.
Development flow
With the EP-1 Series, the only hardware design to be performed by the customer is that regarding the user logic, which is to be mounted onto the gate array. The connection design of the microcontroller and gate array, test design, and package design are performed and checked by NEC Electronics in advance. The customer, therefore, can focus on the software development of the user logic and microcontroller, for differentiation from competitors.
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Development environment
The user logic section can be developed by using the gate array design environment and the software of the CPU section can be developed by using the V850 microcontroller development tools. An evaluation board is also available.
- User logic section design environment
- EP-1 Series on-chip CPU (V850E2 core) software development tools
- EP-1 Series evaluation board
Software development tools
A sophisticated debug environment that supports tracing is available.
Third-party tools can also be used.
EP-1 Series evaluation board
This evaluation board enables the development of the gate array section using an FPGA as well as advance verification close to that of an actual chip.
- Covering with a single unit the functions equivalent to an EP-1 Series-dedicated microcontroller combined with a gate array as well as the configuration of an external general-purpose memory
- Mounting on-board an FPGA that easily covers the size of an ASIC that can be mounted onto a PFESiP
- Xilinx Virtex-4 is employed.
- It can be selected among XC4VLX40 (standard)/60/80/100/160 through BTO.
- Various on-board memories
- Flash ROM, SRAM, SDRAM
- SRAM and SDRAM support both 32- and 16-bit data buses.
- On-chip USB 2.0 FS Host/Function and UART connectors (× 4)
- Wealth of expansion connectors
- For EP-1 Series-dedicated microcontroller general-purpose boards:
- 80 signals (general-purpose 50-pin connector × 2)
- For FPGA GPIO:
- 240 signals (MICTOR connector × 3)
- 80 signals (general-purpose 50-pin connector × 2)
- Dedicated for MEMC buses:
- 91 signals (MICTOR connector × 1)
- For EP-1 Series-dedicated microcontroller general-purpose boards:
