Primary Specifications for NEC Electronics' µPD78F8056, µPD78F8057, and µPD78F8058

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Item		µPD78F8056	µPD78F8057	µPD78F8058
Internal memory	Flash memory (self-programming supported)	64 KB	96 KB	128 KB
	RAM	8 KB Note 1	8 KB Note 1	8 KB Note 1
Memory space		1 MB
Main system clock (Oscillation frequency)	High-speed system clock	X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) 2 to 20 MHz: VDD = 2.7 to 3.6 V, 2 to 5 MHz: VDD = 1.8 to 3.6 V
	Internal high-speed oscillation clock	Internal oscillation 1 MHz (TYP.), 8 MHz (TYP.): VDD = 1.8 to 3.6 V
	20 MHz internal high-speed oscillation clock	Internal oscillation 20 MHz (TYP.): VDD = 2.7 to 3.6 V
Subsystem clock (Oscillation frequency)		XT1 (crystal) oscillation 32.768 kHz (TYP.): VDD = 1.8 to 3.6 V
Internal low-speed oscillation clock (dedicated to WDT)		Internal oscillation 30 kHz (TYP.): VDD = 1.8 to 3.6 V
General-purpose register		8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time		0.05 µs (High-speed system clock: fMX = 20 MHz operation)
		61 µs (Subsystem clock: fSUB = 32.768 kHz operation)
Instruction set		- 8-bit operation, 16-bit operation - Multiplication (8 bits × 8 bits) - Bit manipulation (Set, reset, test, and Boolean operation), etc.
I/O port		Total:18Note 2 CMOS I/O: 13 Note 2 CMOS input: 4 Note 2 CMOS output: 1 Note 2
2.4 GHz RF transceiver		IEEE 802.15.4-2006 compliance (modulation system: O-QPSK, spreading system: DSSS, data rate: 250 kbps)
Timer		- 16-bit timer: 12 channels (unit 0: 8 channels, unit 1: 4 channels) - Watchdog timer: 1 channel - Real-time counter (RTC): 1 channel
	Timer output	2 (PWM outputs: 2 Note 3 (timer array unit 0), 0 (timer array unit 1)
	RTC output	1 - 512 Hz, 16.384 kHz, or 32.768 kHz (subsystem clock: fSUB = 32.768 kHz)

Note1.  This is 7 KB when the self-programming function is used.
      2.  Including pins used by the user to externally connect the MCU and RF transceiver on the board.
      3.  The number of outputs varies, depending on the setting.

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Item		µPD78F8056	µPD78F8057	µPD78F8058
Serial interface		- CSI: 1 channel (used exclusively for internal communication with the 2.4 GHz RF transceiver) - CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel - UART (Transmission only) : 1 channel - UART supporting LIN-bus: 1 channel
Multiplier/divider		16 bits × 16 bits = 32 bits (multiplication) 32 bits ÷ 32 bits = 32 bits (division)
DMA controller		2 channels
Vectored interrupt sources	Internal	27
	External	4
Reset		- Reset by pin - Internal reset by watchdog timer - Internal reset by power-on-clear - Internal reset by low-voltage detector - Internal reset by illegal instruction execution Note 1
Power-on-clear circuit		- Power-on-reset: 1.61 ±0.09 V - Power-down-reset: 1.59 ±0.09 V
Low-voltage detector		1.91 V to 3.45 V (11 stages)
On-chip debug function		Provided
Power supply voltage		VDD = 1.8 to 3.6 V
Operating ambient temperature		TA = —40 to +85
Package		56-pin plastic QFN (8 × 8) (0.5 mm pitch)

Note1.The illegal instruction is generated when instruction code FFH is executed.
        Reset by the illegal instruction execution not issued by emulation with the on-chip debug emulator.