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Outline of Functions

Item		78K0R/KF3-L (80-pin)			78K0R/KG3-L (100-pin)
Internal memory	Flash Memory (KB)	64	96	128	96	128
	RAM (KB)	4	6	8^{(Note 1)}	6	8^{(Note 1)}
Memory space		1 MB
Main system clock	High-speed system clock	X1 (crystal/ ceramic) oscillation, external main system clock input (EXCLK) 2 to 20 MHz: V_DD = 2.7 to 5.5 V, 2 to 5 MHz: V_DD = 1.8 to 5.5 V
	Internal high-speed oscillation clock	Internal oscillation 1 MHz±5% (target), 8 MHz±1% (target): V_DD = 1.8 to 5.5 V
	20 MHz internal high-speed oscillation clock	Internal oscillation 20 MHz±1% (target): V_DD = 2.7 to 5.5 V
Subsystem clock		XT1 (crystal) oscillation 32.768 kHz (TYP.): V_DD = 1.8 to 5.5 V
Internal low-speed oscillation clock (dedicated to WDT)		Internal oscillation 30 kHz (TYP.): V_DD = 1.8 to 5.5 V
General-purpose register		8 bits x 32 registers (8 bits x 8 registers x 4 banks)
Minimum instruction execution time		0.05 µs (High-speed system clock: f_MX = 20 MHz operation)
		61 µs (Subsystem clock: f_SUB = 32.768 kHz operation)
Instruction set		8-bit operation, 16-bit operation Multiplication (8 bits x 8 bits) Bit manipulation (Set, reset, test, and Boolean operation), etc.
I/O	Total	71			89
	CMOS I/O	62			80
	CMOS input	4			4
	CMOS output	1			1
	N-ch open-drain I/O (6 V tolerance)	4			4
Timer		• 16-bit timer : 12 channels • Watchdog timer : 1 channel • Real-time counter : 1 channel
	Timer outputs	12 (PWM output: 10^{(Note 2)})
	RTC outputs	2 • 1 Hz (subsystem clock: f_SUB = 32.768 kHz) • 512 Hz or 16.384 kHz or 32.768 kHz (subsystem clock: f_SUB = 32.768 kHz)
Clock output/ buzzer output		2 • 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (peripheral hardware clock: f_MAIN = 20 MHz operation) • 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (subsystem clock: f_SUB = 32.768 kHz operation)
10-bit resolution A/D Converter (AVREF = 1.8 to 5.5 V)		12 channels			16 channels
Serial Interface		• CSI: 2 channels/ UART: 1 channel • CSI: 1 channel/ UART: 1 channel/ simplified I²C: 1 channel • CSI: 1 channel/ UART: 1 channel/ simplified I²C: 1 channel • UART (LIN-bus supported): 1 channel • I²C bus: 1 channel
Multiplier/ divider		• 16 bits x 16 bits = 32 bits (multiplication) • 32 bits ÷ 32 bits = 32 bits (division)
DMA controller		2 channels
Item		78K0R/KF3-L (80-pin)			78K0R/KG3-L (100-pin)
Vectored interrupt Sources	Internal	33
	External	13
Key interrupt		8 channels (KR0 to KR7)
Reset		• Reset by pin • Internal reset by watchdog timer • Internal reset by power-on-clear • Internal reset by low-voltage detector • Internal reset by illegal instruction execution^{(Note 3)}
Power-on-clear circuit		• Power-on-reset: 1.61±0.09 V • Power-down-reset: 1.59±0.09 V
Low-voltage detector		1.91 V to 4.22 V (16 stages)
On-chip debug function		Provided
Power supply voltage		V_DD = 1.8 to 5.5 V
Operation ambient temperature		TA = -40 to +85
Package		80-pin plastic LQFP (14 x 14) (0.65 mm pitch) 80-pin plastic LQFP (fine pitch) (12 x 12) (0.5 mm pitch)			100-pin plastic LQFP (14 x 20) (0.65 mm pitch) 100-pin plastic LQFP (fine pitch) (14 x 14) (0.5 mm pitch)

(Note 1)

This is 7 K bytes when the self programming function is used.

(Note 2)

The number of outputs varies, depending on the setting.

(Note 3)

The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip debug emulator.

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