Item

78K0R/KC3-L (44-pin)
(µPD78F100y^{Note 1}:y = 0 to 3)

78K0R/KC3-L (48-pin)
(µPD78F100y^{Note 1}:y = 1 to 3)

78K0R/KD3-L
(µPD78F100y^{Note 1}:y = 4 to 6)

78K0R/KE3-L
(µPD78F100y^{Note 1}:y = 7 to 9)

Internal memory

Flash memory (KB)

16

32

48

64

32

48

64

32

48

64

32

48

64

RAM (KB)

1

1.5

2

3/2^{Note 2}

1.5

2

3/2^{Note 2}

1.5

2

3/2^{Note 2}

1.5

2

3/2^{Note 2}

Memory space

1 MB

Main system clock

High-speed system clock

X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
2 to 20 MHz: V_DD = 2.7 to 5.5 V, 2 to 5 MHz: V_DD = 1.8 to 5.5 V

Internal high-speed oscillation clock

Internal oscillation
1 MHz±5 %, 8 MHz±1 % (target): V_DD = 1.8 to 5.5 V

20 MHz internal high-speed oscillation clock

Internal oscillation
20 MHz±1 % (target): V_DD = 2.7 to 5.5 V

Subsystem clock

XT1 (crystal) oscillation
32.768 kHz (TYP.): V_DD = 1.8 to 5.5 V

Internal low-speed oscillation clock (dedicated to WDT)

Internal oscillation
30 kHz (TYP.): V_DD = 1.8 to 5.5 V

General-purpose register

8 bits × 32 registers (8 bits × 8 registers × 4 banks)

Minimum instruction execution time

0.05µs (High-speed system clock: f_MX = 20 MHz operation)

0.125µs (Internal high-speed oscillation clock: f_IH = 8 MHz (TYP.) operation)

61µs (Subsystem clock: f_SUB = 32.768 kHz operation)

Instruction set

•8-bit operation, 16-bit operation
•Multiplication (16 bits × 16 bits)
•Bit manipulation (Set, reset, test, and Boolean operation), etc.

I/O port

Total

37

41

45

55

CMOS I/O

33

34

38

48

CMOS input

4

4

4

4

CMOS output

-

1

1

1

N-ch open-drain I/O (6 V tolerance)

-

2

2

2

Timer

•16-bit timer: 8 channels
•Watchdog timer: 1 channel
•Real-time counter (RTC): 1 channel

Timer output

8 (PWM output: 7^{Note 3})

RTC output

2
•1 Hz (subsystem clock: f_SUB = 32.768 kHz)
•512 Hz, 16.384 kHz, or 32.768 kHz (subsystem clock: f_SUB = 32.768 kHz)

Clock output/buzzer output

-

1

1

2

•2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(peripheral hardware clock: f_MAIN = 20 MHz operation)
•256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: f_SUB = 32.768 kHz operation)

10-bit resolution A/D converter (AV_REF = 1.8 to 5.5 V)

10 channels

11 channels

11 channels

12 channels

Serial interface

•CSI: 2 channels/UART (LIN-bus supported): 1 channel
•CSI: 1 channel/UART: 1 channel/simplified I²C: 1 channel

I²C bus

-

1channel

1channel

1channel

Multiplier/divider

•16 bits × 16 bits = 32 bits (multiplication)
•32 bits ÷ 32 bits = 32 bits (division)

DMA controller

2 channels

Vectored interrupt sources

Internal

24

25

25

25

External

9

Key interrupt

6 channels (KR0 to KR5)

8 channels (KR0 to KR7)

Reset

• Reset by pin
•Internal reset by watchdog timer
•Internal reset by power-on-clear
•Internal reset by low-voltage detector
•Internal reset by illegal instruction execution^{Note 4}

Power-on-clear circuit

•Power-on-reset: 1.61±0.09 V
•Power-down-reset: 1.59±0.09 V

Low-voltage detector

1.91 V to 4.22 V (16 stages)

On-chip debug function

Provided

Power supply voltage

V_DD = 1.8 to 5.5 V

Operating ambient temperature

T_A = -40 to +85

Notes 1  

Under development

2  

This is 2 KB when the self-programming function is used.

3  

The number of outputs varies, depending on the setting.

4  

The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator.