NEC Electronics Announces On-chip ESD Protection for the 45-nm Node

Innovative ESD Circuit Structure Enables More Reliable SoC Devices

NEC Electronics today announced that is has developed new technology to protect sensitive semiconductor devices from damaging electrostatic discharge (ESD) pulses. Applicable to the next-generation 45-nm node, the new technology will make system-on-chip (SoC) devices more reliable across a wide range of applications.

NEC Electronics has long been aware of the importance of ESD protection. It has an active research program in this area, focusing on on-chip ESD circuitry for the I/O blocks of general-purpose and high-speed communications devices, and on internal ESD protection in complex devices that consist of numerous functional blocks, such as low-power logic and analog circuits. The newly developed technology relates to ESD protection for general-purpose I/O blocks, which can become gateways for damaging electrostatic pulses from the operating environment and peripherals. When combined with other ESD protection technologies developed at NEC Electronics, it is expected to make a major contribution to increasing the reliability of advanced SoCs at the 45-nm node and beyond.

The new technology improves the performance of the ESD protection circuits found in the I/O block of a SoC. These circuits are comprised of MOS (Metal Oxide Semiconductor) transistors and resistors. The new technology is primarily an enhancement of the resistor structure.

In MOS ESD protection circuits, devices called "ballast resistors" must be placed near the transistors in order to ensure uniform operation across an array of many transistors. Resistance in ballast resistors is provided by a diffusion zone, and a process step called silicide blocking is generally employed to prevent a low-resistance silicide layer from forming over the diffusion zone. However, this approach has the drawback that a large area is required to provide the resistance necessary for uniform operation. This increases the distance between the transistors and makes it difficult to design smaller circuits.

The key innovation in the new technology is a new 3D structure that serves as alternative to silicide blocking. This 3D structure is a contact structure between the transistor and the interconnect which functions as a ballast resistor. It requires no additional process steps and allows the distance between transistor arrays to be shrunk to 1/3 of their previous distance. Resistance characteristics are large and predictable, and the basic contact structure is applicable to both the 45-nm and 32-nm process nodes, making the new technology a leading candidate for application in 45-nm and smaller SoCs from NEC Electronics.

Another innovation relates to heat dissipation. Heat is generated when the protective circuits are activated, and reducing the distance between transistors can cause heat to be trapped within the transistors, damaging their delicate internal structures. To prevent this, resistance in the ballast was reduced, and covered with metal wiring to improve heat dissipation. This structural enhancement resulted in an improvement of up to about 30% in ESD performance, which in turn allowed the size of the I/O block to be shrunk to about 2/3 of the previous silicide block type. This corresponds to 2 to 3% of the total chip area.

Because of the shrinking geometries of SoCs at the 65-nm node and smaller, voltage and current tolerances at the circuit level have become ever more stringent. But smaller geometries require the same level of ESD protection as larger ones. In addition, smaller geometry chips typically integrate a larger number of functional blocks, which creates a new requirement for ESD protection between blocks. These and other factors mean that ESD protection is becoming an increasing important part of SoC design.

NEC Electronics was early to recognize on-chip ESD protection as a vital technology for its advanced SoC products. Since 1999, it has pioneered a number of innovative technologies, such as the CMOS compatible vertical bipolar ESD protection device announced at the 2000 IEDM (International Electron Devices Meeting) in the United States. Especially since the advent of 90-nm products it has introduced numerous innovations, with a focus on three areas of research: compact ESD protection circuitry for general-purpose I/O blocks, low-capacitance and low-voltage ESD protection circuitry for I/O blocks in high-speed communications applications, and inter-block ESD protection circuitry for whole chip protection of SoCs.

The newly developed technology is applicable to ESD protection circuitry for standard-speed I/O blocks such as those found in DDR2 *1 and LVDS *2 applications. It has already been designed into a number of products and is generally applicable for devices fabricated at 45-nm and subsequent process nodes.

NEC Electronics regards the recent innovation as a core component of its ESD protection technology and is working now to introduce it in stable volume production processes. The new technology will be presented at the 29th Annual International EOS/ESD Symposium and Exhibits forum, to be held from September 16 through 21 in Anaheim, California.

*1: DDR2 - Double Data Rate2 memory interface
*2: LVDS - Low Voltage Differential Signaling

About NEC Electronics

NEC Electronics Corporation (TSE: 6723) specializes in semiconductor products encompassing advanced technology solutions for the high-end computing and broadband networking markets, system solutions for the mobile handset, PC peripherals, automotive and digital consumer markets, and platform solutions for a wide range of customer applications. NEC Electronics Corporation has 24 subsidiaries worldwide including NEC Electronics America, Inc. (www.am.necel.com) and NEC Electronics (Europe) GmbH (www.eu.necel.com). For additional information about NEC Electronics worldwide, visit www.necel.com.