Process

50-nm gate length silicon gate CMOS,
All-Cu interconnects 6-layer / 7-layer

Max. available gates

100 million

Max. I/O

2800^*

Power supply voltage

Internal: 1.0 - 1.2V
I/O: 1.8V/2.5V/3.3V

Power consumption

Approx. 1.7 nW/MHz/gate

Delay time

11.8 ps (2NAND,FO=2)

Memory macro

Single/dual/multi-port SRAM
ROM
Register file

Interface

1.8V/2.5V/3.3V interface
Low noise buffer
High-speed interface (LVDS, SubLVDS, SSTL2, SSTL18 et. al.)

IP cores

PLL, A/D converter, D/A converter,
USB2.0, JPEG, DDR/DDR2 SDRAM interface,
CPU, SDIO interface, etc.

Packaging

FPBGA, PBGA, FCBGA