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NEC Electronics Provides Highly Accurate Copper-Interconnect Modeling Methodology
- New design flow enables high-precision wiring delay estimation -
KAWASAKI, Japan, SANTA CLARA, Calif. and DUESSELDORF, Germany, June 11, 2003 -
NEC Electronics Corporation and its subsidiaries in the United States and Europe, NEC Electronics America, Inc. and NEC Electronics (Europe) GmbH, today announced the development of a new, highly accurate copper-interconnect modeling methodology, which will be indispensable for future high-performance, deep-submicron (DSM) semiconductor chip designs. This methodology enables accurate layout parameter extraction (LPE) of copper interconnect and achieves high-precision wiring delay estimation.
The new modeling is a key technology for 90nm-generation designs and beyond. With this modeling, parameter extraction inaccuracy due to copper-interconnect shape variance is effectively compensated, allowing the precision of wiring-delay estimation to be significantly improved compared to the existing technology (more than a 10 percent improvement). Analysis of crosstalk or other interconnect-related design factors can be performed with high accuracy, leading to prevention of signal-integrity issues.
In this new methodology, NEC Electronics adopts the concept of effective density (Deff) and implements a calculation procedure in an electronic design automation (EDA) tool. Deff designates the effective interconnect density of an arbitrary point on the die. Using this parameter, the thickness of the copper interconnect, which has a strong dependence on the surrounding interconnect density, can be universally expressed.
Another notable feature of this methodology is its cost-effective interconnect cross-section modeling parameter extraction. This includes correlating interconnect cross-section observation results with resistance measurements using the newly devised test structures. Consequently, the need for extensive cross-section observation, a time-consuming and expensive task, has been minimized. With this methodology, practical cross-section parameters extraction becomes possible. Using the new model, significant improvement has been confirmed in the accuracy of wiring-induced circuit delay estimation.
"As semiconductor design complexity soars with advances in process generation, interconnect characteristics variance and signal-integrity emerge as clear and present issues that need to be solved," said Kazu Yamada, general manager, Technology Foundation Development Division, NEC Electronics Corporation. "Being the first company to implement this new modeling methodology, we can now offer one of the most precise DSM design environments currently available."
The performance requirement for high-speed computer and network servers continues to rise as these systems form the foundation of next-generation broadband networking. For such high-performance systems, leading-edge design is a mandatory requirement. Such design requires high-precision timing analysis, involving interconnect capacitance and resistance extraction based on a simple three-dimensional interconnect shape model.
However, in the conventional model LPE, the size or shape dependence on interconnect line/space width and density was not incorporated. The influence of such interconnect shape variance had to be handled as "unknown excess margin." As a result, a large excess design margin was required to cover conventional LPE inaccuracy. This means that the circuit design cannot take full advantage of the potential of the advanced process. Also, the excess design margin increases the design turnaround time for timing-closure completion.
To solve this dilemma, NEC Electronics has developed this modeling methodology for high-precision wiring-delay estimation. The company regards the modeling methodology as a vital technology for competitive leading-edge deep submicron (DSM) design and has implemented it in its standard 90-nanometer design flow.
NEC Electronics will reveal the details of this new modeling methodology on June 11 at the 2003 Symposium on VLSI Technology (June 10-12), session 8B-4, in Kyoto, Japan.
About NEC Electronics Corporation
NEC Electronics worldwide specializes in semiconductor products encompassing advanced technology solutions for the high-end computing and broadband networking markets, system solutions for the mobile handsets, PC peripherals, automotive and digital consumer markets, and platform solutions for a wide range of customer applications. NEC Electronics Corporation has 24 subsidiaries worldwide including NEC Electronics America, Inc. (www.am.necel.com) and NEC Electronics (Europe) GmbH (www.ee.nec.de).
In addition to marketing, selling and supporting NEC Electronics products to customers in their respective regions, NEC Electronics America and NEC Electronics Europe also operate local manufacturing facilities in Roseville, California, and Ballivor, Ireland, respectively. The two companies also serve as the sales and marketing channels of NEC AM-LCD and PDP modules in North America and Europe, respectively. For additional information about NEC Electronics worldwide, visit www.necel.com. NEC Electronics Corporation is a wholly owned subsidiary of NEC Corporation (NASDAQ: NIPNY) (FTSE: 6701q.l), one of the world's leading providers of Internet, broadband network and enterprise business solutions.
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