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Line Buffer

Overview

A FIFO (first-in, first-out) type memory ideal for line delay and time axis conversion in equipment such as facsimiles and digital copiers.

Features

Different cycles enabling independent and asynchronous writing and reading

Lineup

Density Part Number 80K µPD485506 40K µPD485505

AdvancedParametric

Memory Home

• Product Lineup
  • Static RAM (SRAM)
  • Low Letency DRAM
  • Mobile Specified RAM
  • Mask ROM
  • Stacked MCP
  • Line Buffer
  • Line Buffer
    • [80K/40K]
• Design Information
  • Simulation Models
• Documentation
  • Static RAM (SRAM)
  • Low Latency DRAM
  • Mobile Specified RAM
  • Mask ROM
  • Stacked MCP
  • Line Buffer
• Part Number Guide
  • [µPD23Cxxx]
  • [µPD43xxx]
  • [µPD44xxx]
  • [µPD46xxx]
  • [µPD48xxx]
  • Memory Product Part Numbers
• Phased Out Products
  • Standard Synchronous SRAM 8M bit
  • Late Write Synchronous SRAM 8M bit
  • Late Write Synchronous SRAM 32M bit
  • ZEROSB SRAM 8M bit
  • ZEROSB SRAM 32M bit
  • Mask ROM