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Volume 77 (Mar 26, 2008)
Taking advantage of the allure of PFESiP: new ASIC solution combines a microcontroller and gate array in SiP
A new ASIC solution that encapsulates a dedicated 32-bit V850E2™ CPU core-based microcontroller and a gate array in a single package has made its debut. This new ASIC not only aids in shortening development time and cost, it also reduces both the number of components and the size of the mounting area. We interviewed members of the Platform for embedded system-in-a-package (PFESiP) development team to get the story behind its development.
How did you come up with the idea of combining a microcontroller and a gate array in a SiP?
Suzuki: We found through research we conducted to prepare for development of this new ASIC product that wherever you find an ASIC, there is bound to be a microcontroller. And with system-on-a-chip (SoC) technology, a microcontroller and ASIC can be integrated to form a single silicon chip. When it came to actual market needs, however, many customers mentioned that they would like to have the option of being able to customize a little when using a microcontroller. We therefore decided to combine a microcontroller with a gate array capable of being easily customized with microcontroller peripherals that, in turn, would allow us to easily offer customized microcontrollers.
Furuki: While it is possible to freely design an SoC using a cell-based IC, this option can lead to increased development costs, which is why we wanted to provide an alternative that would still offer users freedom of design. Even for customers who have up until now used microcontrollers and gate arrays separately, PFESiP offers the advantage of a single package that makes it possible to reduce both the number of components and the size of the mounting area at a low cost.
Takakura: It can be said that NEC Electronics was able to come up with an innovative concept like this due to our wealth of experience in the development of both microcontroller and gate array products. I also believe that our history of developing not only gate arrays but also numerous SoCs greatly contributed to the successful development of this product.
What are some of the ingenuity that went into the development of PFESiP?
Suzuki: We began by developing a PFESiP-dedicated microcontroller and a dedicated gate array master. Then we optimized the pin layout, design, size, and so forth so that we could directly connect the microcontroller and gate array master using a gold wire, thereby creating a system in a package (SiP). To facilitate final timing verification by customers, the basic timing of electrical signals between the microcontroller and gate array are guaranteed by NEC Electronics. In addition, to render verification of interface noise by customers unnecessary, our company carries out highly precise verification suitable even for high-end products prior to delivery to customers. This means that the only circuit customers need to develop on their own is the logic part of the gate array, which in turn makes it possible to reduce the man-hours necessary for device design and verification as well as development time.
Furuki: We also thoroughly analyzed and verified thermal resistance, electrical specifications and reliability to provide our customers with greater peace of mind. In addition, since it is said that fitting a microcontroller and an ASIC into a single package via the SiP method would involve 1.5 times the cost of combining the two separately, we focused our efforts on creating a package that would allow us to keep costs low.
Mita: To enable our customers who had up until now used our V850™ microcontrollers to continue using their existing software assets with this new product, we developed a dedicated microcontroller based on the V850E2 core.
Takakura: And to make it even easier for our customers to use embedded memory, we decided to increase the amount of memory to 192 KB and improve performance. While the flash memory is external, speed can be further increased if the memory is internal. This kind of ingenuity was also integral to reducing the number of components and cutting development costs.
What application fields are being targeted for PFESiP?
Furuki: During the planning stages for PFESiP, we spoke with customers who were already using our microcontrollers and gate arrays separately, and through these discussions discovered that the number one request was for microcontroller performance in the neighborhood of an operating frequency of 200 MHz. Customer needs appear to be highest in the industrial markets (servo motors, inverters, vending machines, etc.) and in office equipment applications (printers, etc.), and we therefore have very high hopes for these sectors.
Mita: As for PFESiP product expansion, we currently have plans in the works to take the CPU from 200 MHz to the 100 to 150 MHz band to achieve even lower power consumption, and to the 266 MHz band to enable operation at higher speeds. Since our customers' sets also include a wide variety of product lineups, I believe that platformization will be the key word in the future for both our customers' sets and our own products.
Thank you for speaking with us today.
A new ASIC solution like no other that has come before it. Look to NEC Electronics to take this technology even further.
Experiencing PFESiP through a demonstration!
Demonstration by a developerImage display transmission via a microcontroller serving as a logic circuit with an added LCD controller function was demonstrated using a PFESiP evaluation board in November at Embedded Technology 2007 in Japan.
"JPEG data from the function board is transmitted to the PFESiP-mounted board via the USB. The transmitted JPEG data then passes through the SDRAM, is decoded by the PFESiP microcontroller and is then displayed on the LCD panel using the LCD controller function burned onto the FPGA."
Volume 78
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