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Volume 72 (Oct 29, 2007)

Summary of NEC Electronics Papers Presented at the 2007 EOS/ESD Symposium (2/3)

Layout Technique to Alleviate Soft Failure for Short-Pitch Multi-Finger ESD Protection Devices

A high-performance, low-cost MOS-type electrostatic discharge (ESD) protection device has been developed featuring two layout modifications that significantly reduce soft failures—a short-pitch multi-finger layout using a contact ballast resistor and a heat dissipation path.

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MOS-type electrostatic discharge (ESD) protection devices require a ballast resistor to ensure uniform triggering of all transistors in a multi-finger layout. The most common way ballast resistors have been implemented is through silicide blocking that prevents silicidation of the diffusion layer, which can be done by adding additional process steps to the standard CMOS process. The main problem with this approach is that it increases the spacing between transistors (that is, the pitch), thus making it difficult to reduce the area. We came up with a better solution by implementing the ballast resistor as a contact called contact ballast (CTB) resistor, and by developing a short-pitch multi-finger layout technique that is only one-half to one-third the size of conventional layouts (Figure 1).

Adopting the short-pitch multi-finger layout technique ensures uniform sequential triggering of adjacent fingers of a multi-finger MOS device when an ESD event occurs. One drawback of these short-pitch multi-finger implementations is that the current does not flow uniformly within the transistors, which makes it difficult to ensure uniform triggering for the device as a whole. Because transistors are crowded closer together, heat dissipation to the direction vertical to the transistors or to the direction of the substrate is restricted, which causes localized current hot spots that result in transistor soft failures (Figure 2).

In recent work, we modified the layout of the device to address this problem by reducing part of the ballast resistor to ensure a viable heat dissipation path and by adding some additional metal parallel to the transistors (Figures 3 and 4). These modifications not only reduced the incidence of soft failures but also improved ESD performance by 17% to 30% without increasing the area of the device (Figure 5).

These new techniques open the way to development of cost-priority general interface circuits that are area efficient, and to better- performing DDR2 (*1), LVDS (*2), and other kinds of high-speed interface circuits by reducing the capacitance of the ESD protection devices. In addition, internal submicron thin-film transistors are protected from breakdown by low clamping voltage by the low on-resistance characteristic. These ESD protection circuits have already been applied as core components of our ESD technology in NEC Electronics 90-nanometer (nm) to 55 nm node system LSI chips.

NEC Electronics is committed to making further progress in the development of advanced ESD protection technologies for system LSI products.

From engineer

We have developed a high-performance, low-cost MOS-type electrostatic discharge (ESD) protection device that can be incorporated in a wide range of system LSI chips. During development, serious challenges were faced in deriving temperature characteristics of transistors over time using three-dimensional simulation tools, but numerous incremental improvements finally led to the development of this high-performance protection device. The device has already been applied to some 90 nm to 55 nm node process products. In collaboration with other divisions, we will continue to build on this work to boost performance even more, develop a wider range of products, and apply ESD protection devices to other system LSI chips and process nodes.

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