Volume 70 (Aug 24, 2007)

How a change in thinking led to the development of our low standby power CMOS technology and the story behind the birth of "ultra-thin high-k theory"

NEC Electronics has developed a 55-nanometer (nm) cell-based integrated circuit (IC) capable of dramatically reducing power consumption. Utilized in this IC is a low standby power CMOS technology that supports extended battery usage in mobile phones and other portable devices. We asked the developers of the first practical application of high-k gate insulation film to discuss their journey to make ultra-thin high-k a reality.

The developers of the high-k gate insulation film transistor
Top row, left to right:
Kiyotaka Imai, Group Manager, Advanced Device Development Division
Yasushi Nakahara, Senior Process Engineer, Advanced Device Development Division
Toru Tatsumi, Senior Principal Researcher, NEC Central Research Laboratories
Ichiro Yamamoto, Senior Process Engineer, Process Technology Division
Bottom row, left to right:
Toshiyuki Iwamoto, Assistant Manager, Advanced Device Development Division
Tomohisa Abe, Assistant Manager, Advanced Device Development Division
Tadashi Fukase, Team Manager, Advanced Device Development Division

How can the driving ability of a low standby power CMOS transistor be further improved?

One of the issues we faced was how to further improve the driving ability of a low standby power CMOS transistor—the power consumption of which is low during standby operation—to enable both enhanced performance of and reduced power consumption in portable devices. In the past, our aim had been to improve transistor driving ability by reducing the thickness of gate insulation film. However, the silicon oxynitride film (SiON) conventionally used as a gate insulation film caused increased gate leakage current, and reduction of the thickness of the film had already reached its limit. Therefore, around the year 2000, we began development of a gate insulation film with a high dielectric constant (high-k) in order to reduce gate leakage current. This is because high-k possessed a special characteristic that enabled improvement of ON current by decreasing gate leakage current and electrically reducing the thickness of gate insulation film.

We focused on hafnium (Hf) as a new material for creating the high-k gate insulation film. With the vast array of high-k materials available, electron mobility degradation became an issue. The use of hafnium leads to the suppression of electron mobility degradation, thereby resulting in improvement of transistor performance. This is why we became engaged in the development of a high-k gate insulation film that could be used to form a hafnium silicate film on silicon dioxide film. However, controlling the formation of thin silicate film was difficult and things did not go according to plan at first. However, after repeatedly carrying out material verification, we were able to successfully develop a hafnium silicate (HfSiOx) film having favorable interface stability with silicon (Figure 1).

Because HfSiOx film had little mobility degradation compared to other gate insulation films and because of its excellent reliability, our expectations for its commercialization were high. Full-blown implementation of trial production equipment began immediately, followed by the commencement of system LSI development. In terms of device performance, however, although NMOS performance was tremendously favorable, PMOS performance did not achieve mass-production criteria. Unfortunately, after a number of test trials, we were unable to obtain satisfactory characteristics.

As we found ourselves groping blindly in the dark, we learned about a phenomenon referred to as Fermi-level pinning that had been presented at an academic conference. Fermi-level pinning is a phenomenon in which the threshold voltage increases dramatically when the components of hafnium silicate (HfSiOx) film, that is hafnium (Hf), silicon (Si) and oxygen (O), are combined (Figure 2) and the driving ability of the transistor declines. Until this point, we had worked hard to increase the dielectric constant by increasing the amount of hafnium in order to reduce gate leakage current, but then we realized that the bottleneck prohibiting us from achieving commercialization was in fact due to the Fermi-level pinning effect.

A change in thinking: Focusing on not only electrically reducing the thickness of gate oxidation film, but also improving NMOS characteristics

At that point, by shifting our attention to the threshold voltage, we were able to devise a new theory in which the amount of hafnium is decreased to suppress the increase of the threshold voltage. Moreover, we began to consider controlling the threshold voltage by using the Fermi-level pinning phenomenon—with which mobility can be improved even with miniscule amounts of hafnium—to our advantage. Traditionally, control of the threshold current had been carried out by changing the concentration of channel impurities. However, what we were aiming toward was control of the threshold current by decreasing the concentration of channel impurities and also by using hafnium. Thanks to this new method, our research findings showed that it was possible to improve mobility, reduce junction leakage current and suppress the narrow channel effect. This led us to formulate the "ultra-thin high-k theory," which hypothesized that a little bit of hafnium would be useful in low-power device technology because hafnium improves the driving ability of transistors (Figure 3). Thereafter, team members from the Process Technology Division and NEC Central Research Laboratories began to see a glimmer of hope for achieving commercialization and embarked on joint development of a 55-nanometer (nm) process technology using this technology.

During process development, we found ourselves wondering how much hafnium we would need to attain a reasonable threshold voltage. In addition, how could we produce controllability using just a little bit of hafnium in order to improve the performance of NMOS and PMOS in a balanced manner? Trial production of and experiments on the hafnium-dioxide silicate film were repeatedly carried out. Although everything was going well with the "ultra-thin high-k theory", we faced even more hardships.

As a result of trial and error, we were able to keep the increase in the threshold value between 0.2V and 0.25V by using a hafnium-silicate film for which the amount of hafnium was reduced to one-tenth the amount conventionally used. By using this miniscule amount of hafnium-dioxide silicate, as well as by following this new method in which both work function control and channel impurities are used, we managed to establish threshold voltage settings between 0.3V and 0.5V.

Actual results of the "ultra-thin high-k theory"

During the implementation process of the "ultra-thin high-k theory", we discovered that it had a myriad of advantages. First, costs could be dramatically reduced to just one-tenth of those for high-end processes in which eSiGe is used. In terms of transistor performance, an improvement of 20% or more could be achieved for ON current performance (Figure 4). Moreover, it produced appropriate results as a next-generation process technology, including improvement of yield in cases in which SRAM and DRAM were used together.

Used in 55 nm process cell-based ICs, these technologies not only help achieve low power consumption in portable devices—thereby enabling extended periods of operability, but they also contribute to cost reduction through high integration. NEC Electronics will continue to keep its eye on the diversification and increased functionality of portable devices so as to develop technologies and products that can be used to achieve high-quality image processing in portable devices.

Volume 71

• NEC Electronics Activities in Automotive: AUTOSAR

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