Volume 44 (July 14, 2005)

Concurrent Design Flow for Chips and Packages Shortens Development Period for LSI Products

Development iss

For products such as servers, printers, digital cameras and mobile phones, new models are released one after another, and as a result, product life cycles have become shorter and shorter. Therefore, to get an edge over competitors, it is essential for companies to accelerate their products' time to market. As a result, semiconductor manufacturers have been looking for ways to shorten their development times.

In traditional semiconductor development, chip and package designs created individually and design functions, performance ratings, package sizes, pin counts and optimum buffers verified later to ensure that the products matched customer specifications. When the designs were complete, they were verified and evaluated to find any problems that may have occurred once the chips and packages were assembled (Figure 1). Since this method meant that chip and package specifications were created separately, product characteristics could not be confirmed until after final assembly. If problems were discovered at that stage, an engineer would have to revise the design or change the specifications. This reworking was one of the reasons behind the long development times.

Thus, to complete development in a short period of time, designers must use a highly precise advance verification method capable of ensuring fulfillment of product characteristics once the chips and packages have been assembled.

Concurrent design flow for chips and packages reduces the frequency of reworking an LSI design

NEC Electronics has developed a concurrent design flow capable of virtually verifying post-packaging electrical characteristics at the time a specification is created, making it possible to reduce the frequency of redesigns. In more precise terms, a virtual model of the integrated chip (IC) and package is created, and simulations are carried out to verify electrical characteristics in advance.

An optimum I/O buffer is first selected by taking into account the load conditions of the device. Next, a power source and signal pads are positioned on the chip, and then pins are assigned and connected to the package accordingly. In addition, the wiring length and number of layers of package interposer are estimated, and a virtual model of the IC and package is created. The virtual model is then used to verify electrical characteristics such as impedance and noise (Figure 2). Thanks to these simulations, advance verification can be performed in just a matter of days. If problems are discovered, they can be corrected for optimization during the initial design stage. Through the use of this integrated design environment, the precision and design quality of device specifications can be improved, a significant decline in reworking frequency during the later design stages can be achieved, and the development period can be shortened.

This flow also contributes to the optimization of system levels because models can be reported during the early stages of board design. To eliminate inconveniences related to verification after board design for our customers, we plan to continue developing design environments that take into account each customer's individual board characteristics during initial verification.

In this way, it is possible to carry out highly precise advance verification of both the chip and package design, and realize shorter development periods and accelerated times to market. By freely using the design know-how, characteristics databases and more accumulated over the years, NEC Electronics will continue to act as a best partner for its customers by helping to ease the burden of development and providing support for new product development.

• GENISSNX™ is a trademark of NEC Informatec Systems ,Ltd.

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