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Volume 15 (Nov 07, 2003)
Advanced SoC Joint Research Center Construction Completed at NEC Sagamihara Plant
On June 23, 2003, the opening ceremony of the Advanced System-on-Chip (SoC) Joint Research Center at NEC Sagamihara plant was held by the National Institute of Advanced Industrial Science and Technology (AIST), an incorporated administrative agency. Over 100 people affiliated with the government and semiconductor industry attended the ceremony. President Kaoru Tosaka of NEC Electronics delivered a congratulatory address as chairperson of the Semiconductor Executive Committee for the Japan Electronics and Information Technology Industries Association, Inc. (JEITA).
What is the Advanced SoC Joint Research Center?
Product development using cutting-edge SoC technology such as SoC based on a 90 nm process has reached a point where the burden is too great for industries to handle independently. This is due to increases in development costs and longer development periods. Therefore, the JEITA Semiconductor Executive Committee, made up of Fujitsu, Matsushita Electric Industrial, NEC Electronics, Toshiba, Renesas Technology, Oki Electric Industry, ROHM, Sanyo Electric, Sharp and Sony, has established the Advanced SoC Platform Corporation (ASPLA) to oversee a pilot manufacturing line. This line works to standardize design rules for the 90 nm process, which is promoted by the Semiconductor Technology Academic Research Center (STARC). The committee also investigates the design assets of libraries and intellectual property (IP). Now, with the opening of the Advanced SoC Joint Research Center at NEC Sagamihara plant, we are able to run a pilot and verification line for state-of-the-art LSI devices that employ 90 nm process technology and 300 mm wafers.
NEC Electronics received the contract to build the center under government funding and finalized the transfer to AIST in March 2003. The newly completed center provides a model for cooperation between industrial and academic institutions in conducting joint research. This includes standardizations in fields sharing a common base in both SoC design and production using nanometer design, such as the 90 nm, standard with 300 mm wafers. The center began operating in April 2003 and has already completed operability verification of a trial product that uses copper wire.
In October 2003, ASPLA plan to start IP shuttle services for high-powered generic libraries. Also, in December 2003, ASPLA will offer IP shuttle services for low-powered libraries suitable for mobile and digital consumer products. An IP shuttle service is a service that mounts the chip designs of multiple users on a single wafer. With this service, the semiconductor manufacturer can have lower development costs by dividing the cost according to the area of the wafer used for the chip.
NEC Electronics' Activities
While acting as a development partner helping to standardize 90 nm process design rules and providing design assets such as libraries and IP, NEC Electronics has also been entrusted by ITRI and ASPLA with the maintenance and management of facilities. Moreover, by continuing to work closely with ASPLA, we will develop more cutting-edge semiconductors within a shorter period of time and at a lower development cost.
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