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Volume 2 (Aug 01, 2003)

Facing the Challenge of CB-90 Development (1/2)

Part 1: Process Development

Prologue: Targeting a standard process two generations ahead

One day in 1999, six NEC engineers, including project leader Atsuki Ono, gathered at the Advanced Device Development headquarters in Sagamihara, Japan, to begin development of a 90 nm process technology. Several years later, this group of the best and the brightest would successfully roll out "UX6", the foundation process for CB-90 system LSI design.

Early on, it was generally believed that development of the 90 nm process would be extremely arduous. The majority of LSI vendors were still using 150 to 180 nm process technologies at the time, and it was assumed the next-generation target would be 130 nm. The NEC designers, however, had their sights set two generations ahead.

From the very beginning, the team set out to develop a process that would be recognized as the industry standard for the future. To assure competitiveness from a business standpoint and to strengthen our leadership over other companies, it was crucial that NEC Electronics become the first company to roll out 90 nm.

About the time team members began to doubt the task was achievable, they came up with several brilliant new ideas: new material for the gate electrode combined with a new formation method for gate dielectric film! Silicon samples were fabricated and performance was proven with actual silicon. With this new method, the team finally succeeded.

Breaking through the walls

At the start, nobody knew whether it was feasible to achieve high performance and low power consumption with a single process below 100 nm. The six engineers who boldly set that target found themselves facing great obstacles. Reducing transistor delay time with high drive capability at a power-supply voltage of only 1 volt proved to be difficult enough, but doing so while trying to suppress standby power consumption seemed almost impossible. After a period of trial and error, team members began to wonder whether they had chosen the appropriate transistor-component material in the first place. To suppress leakage current, they decided they would have to develop a new gate dielectric film and gate electrode. Needless to say, the "walls" were closing in.

In general, process development must be completed prior to fabrication of new LSI devices of that generation. The term "process" refers to the technology for printing circuits onto silicon wafers. After process development has been completed, circuit designers can commence actual fabrication and evaluation of their circuits with various functions. In this case, the development team knew too well the need for demonstration with actual silicon as early as possible. Discussions with the circuit design team occurred from the beginning and clear device parameters targets were set so as to pull in the date of announcement and demonstration to the public.

Performance and cost were not the only factors driving the project. Everyone involvedfelt the pressure to develop something that would be recognized as the industry standard. Because of the seeming impossibility of the goal, team members had to overcome enormous resistance, even within the company. They prevailed, and the first wall was broken.

Material selection for the gate electrode: Chasing a new horizon or inheriting existing technology?

Selecting materials for the transistor gate electrode, after finding out that the conventional ones could not deliver the performance targets, was the first major difficulty faced by the project team.

For gate electrodes, poly-crystalline silicon (poly-Si) a semiconductor in a normal state is used as a base material. Then certain impurities are introduced to turn it into a "conductor," enabling the conduction of electricity (Figure 1). These impurities are also introduced into the silicon zone adjacent the gate for source and drain formation.

In following the conventional process for creating microscopic transistors, a decrease in impurity concentration in the vicinity of the gate occurs, and this causes the transistor's characteristics to deteriorate (Figure 2). This deterioration phenomenon did not pose a serious problem in generations above 130 nm and could be disregarded. However, in the realm of the 90 nm process, this deterioration phenomenon was no longer negligible and directly affected transistor characteristics, reliability and hence circuit performance.

The development team made a turning-point decision, in collaboration with the NEC Silicon System Research Center, to introduce silicon germanium (Si-Ge) as the new gate electrode material in addition to Poly-crystalline Si. For practical LSI integration, this was the first attempt in the world and it took a great deal of courage and determination to try it.

The deterioration observed using conventional poly-crystalline Si was effectively dissolved using gate electrode with a stacked structure of poly-crystalline Si and Si-Ge (Figure 3). The use of Si-Ge in addition to poly-crystalline Si also increased the activation ratio of boron impurity in the material, enhancing transistor performance as well. These were the obvious advantages for adopting the new stacked structure.

However, there were still issues to overcome. Germanium source gas (GeH₄) is highly reactive to oxygen and is also said to be extremely harmful to the human body. For this reason, the semiconductor production lines that employ the gas must maintain a low-pressure state relative to the outside environment.

For the process integration, it was necessary to confirm the compatibility with the process flow and carefully check if there were any effects on other elements, such as gate-dielectric film. Introducing the new material put a heavy load on the initial goal of early announcement and demonstration. The adoption of germanium gas and Si-Ge gate electrode inevitably added a fair amount of work and there were many dissident voices arising from such concern.

It was time for a major decision. Would it be more beneficial to take a risk and employ the new material to reap the benefits of improved performance, or would it be wiser to be safe and stick to the existing material? After a few weeks of heated discussion, the team finally decided to take the challenge and resumed work on Si-Ge. From a device perspective, the major issue was to find the optimum structure. Increasing germanium concentration improves transistor performance, but too high of a concentration also degrades ultra-thin gate-dielectric film. Sample fabrications were repeatedly performed to determine the optimum balance. These efforts eventually paid off, and the team obtained a solution satisfying all specifications, including reliability. The paper describing the results was adopted for IEDM2000 and placed in the highlight session.

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