By Year

Along with the demand for fast and beautiful printing of business documents and pictures taken with digital cameras, there are mounting needs for high-resolution color laser printers in a wide spectrum of areas ranging from business to personal use. NEC Electronics has developed a laser control core (pulse-width modulator, or PWM) for cell-based IC use that is essential to further increasing the speed and definition of printers and copy machines. Here we will introduce the capabilities of this laser control core as well as the advantages of its implementation at the time of printer development.

The ZigBee® short distance communication protocol has recently been receiving a great deal of attention. With low cost and low power consumption, ZigBee protocol is an ideal technology for forming a mesh network. This article introduces ZigBee network solutions, which are realized utilizing the NEC Electronics' All Flash microcontrollers.

The ESD Association's annual "2007 EOS/ESD Symposium," a premier international event focused on electrical overstress and electrostatic discharge failures and solutions in electronic devices and parts, was held in Anaheim, California, USA, from September 16—21. Here we will briefly introduce the research findings presented by NEC Electronics engineers at this year's EOS/ESD Symposium.

Since becoming a premium member in AUTOSAR NEC Electronics has also assumed a very active role in the standardization work to build a common platform for software development. AUTOSAR is a consortium made up of vehicle manufacturers, ECU suppliers, and software development tool vendors. We asked an engineer of NEC Electronics Europe about the activities in AUTOSAR.

NEC Electronics has developed a 55-nanometer (nm) cell-based integrated circuit (IC) capable of dramatically reducing power consumption. Utilized in this IC is a low standby power CMOS technology that supports extended battery usage in mobile phones and other portable devices. We asked the developers of the first practical application of high-k gate insulation film to discuss their journey to make ultra-thin high-k a reality.

The "2007 Symposia on VLSI Technology and Circuits"—widely recognized as premiere conferences for presenting research results on the latest device, process, and circuit-related developments—were held this year at the Rihga Royal Hotel in Kyoto, Japan, from June 11 to 16, 2007. Here we will introduce the papers presented by NEC Electronics in collaboration with NEC Corporation.

2007/09/25 "Development of Fundamental New Technologies Enabling Further Digitization of Wireless IP Cores" has been added.

The world's most advanced wiring technology was announced at the IEEE International Interconnect Technology Conference (IITC) 2007, which was held from June 4 to June 6, 2007 in San Francisco, California. Engineers from NEC Electronics and NEC Corporation introduced their joint research results at this year's conference.

To achieve high-resolution display of graphics in cellular phones and other high-end consumer devices, high-speed data processing is certainly required, but larger memory capacity and high-speed data transfers between the processor and memory are also indispensable. In this article, we will introduce SMAFTI, a promising new system-in-package (SiP) architecture that was specifically developed to meet these high-speed data transfer and large memory capacity requirements at low cost.

This is the story of the development of an automotive power MOSFET aimed at attaining a high current output of 160A or more. Here, at last, is the second part of an article we first introduced in 2004 titled, "The path traveled by the creators of the NP Series of ultra-low on-resistance power MOSFETs for automobiles: Breaking the 2 mΩ barrier."

EMI noise is a source of frustration for many electronics manufacturers. This article introduces NEC Electronics' spread-spectrum clock generator (SSCG) macro for on-chips, which—using the concept of incorporating noise reduction functions into the actual LSI itself—realizes superior characteristics.

A powerful statistical modeling-based algorithm has been developed for determining optimal timing design margins to address the challenge of increasing interconnect parameter variations in the development of system LSI chips for the 65-nanometer (nm) node and beyond. The algorithm has now been incorporated in an RC extraction tool and been proven to result in enhanced design capabilities.