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Products > ASIC > Gata Array and Embedded Array > Product Lineup >

EA-9HD Series


The EA-9HD series provides advanced embedded arrays based on a 0.35 µm CMOS process with three or optional four metal layers. This series' high-density, high-speed architecture enables embedded high-density cell-based SRAM blocks. EMI noise is reduced by filling up the empty area of an internal circuit with special capacitor cells and/or by separating the power supply lines of the internal circuit and the I/Os.


Special Features

  • 3.3V supply voltage
  • 5V full-swing I/Os
  • Spread-spectrum clock generator macro to suppress EMI noise

Application

  • medium- or large-size memory embedded
  • 3.3V single-drive medium- or large-scale system
  • Mixed 3.3V and 5V medium- or large-scale system
  • 3.3V single or mixed 3.3V and 5V I/F circuits

Specification

Item Specification
Process 0.35 µm CMOS process
Number of usable gates 9,700 to 1,500,000 gates
Supply voltage 3.3±0.3V, 3.3±0.165V, 3.0±0.3V
Delay time Internal gate 131 ps (F/O=1, typical wire length)
Power gate 107 ps (F/O=1, typical wire length)
Input buffer 229 ps (F/O=2, typical wire length)
Output buffer 1.396 ps (IOL=9 mA, CL=15 pF)
System clock frequency 100 MHz
Output drive capacity IOL=1, 2, 3, 6, 9, 12, 18, 24 mA
Operating ambient temperature TA=-40 to 85°C
I/O buffer 3.3 V type, 5 V full-swing, PCI, GTL+, oscillation block (MHz band, KHz band)
Memory macro -Synchronous high-speed dual-port compiled RAM
-Synchronous high-density single-/dual-port compiled RAM, ROM
Mega macros -Serial control unit
-Programmable timer counter
-Interrupt control unit
-UART
-POR (power-on reset)
Test related SCAN, BSCAN
Other macros CTS, DPLL (for phase control, for multiplication), APLL (for phase control, for multiplication), SSCG

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