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Gate Arrays Development Flow
When actually designing a NEC Electronics Gate Arrays, a design environment (design tool) is needed. As the Gate Arrays design environment, NEC Electronics supports OPENCAD™,which integrates NEC Electronics original tools and commercial tools.
Gate Arrays Development Methods
The flow of Gate Arrays development can be broadly divided into two techniques.
- Circuit diagram input design
A method in which netlist data is created from a circuit diagram, using necessary items from the function block list (library) provided by NEC Electronics. - Top-down design
A method in which the desired circuit structure is functionally described with a specialized language (VHDL, Verilog® HDL, etc.) and converted to netlist data using a logic synthesis tool.
After designing the circuit by one of the above methods, a "test pattern" (expected values data) is used to perform a simulation to verify that the functions and timings achieved by the circuit are as specified.