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Idea 9: Reduce EMI
If your FPGA-based application is too noisy, gate arrays can help reduce the EMI in several ways. First, on-chip capacitance cells can be allocated to any space in the gate array's internal core area. These cells impose no area penalty, and they dampen clock noise significantly. Second, some of our gate arrays include spread-spectrum clock generation circuitry that flattens EMI peaks. Third, our gate arrays are designed to isolate power lines between the core and I/Os. This design helps prevent internal circuit noise from coupling to I/O signals.
