|
Item
|
Specification
|
|
Process
|
0.5 µm CMOS process
|
|
Number of usable gates
|
1,500 to 92,500 gates
|
|
Supply voltage
|
5.0±0.5V, 3.3±0.3V
|
|
Delay time
|
Internal gate
|
0.21 ns (supply voltage: 5.0 V, F/O=1, typical wire length) 0.28 ns (supply voltage: 3.3 V, F/O=1, typical wire length)
|
|
Power gate
|
0.16 ns (supply voltage: 5.0 V, F/O=1, typical wire length) 0.22 ns (supply voltage: 3.3 V, F/O=1, typical wire length)
|
|
Input buffer
|
0.23 ns (supply voltage: 5.0 V, F/O=1, typical wire length) 0.31 ns (supply voltage: 3.3 V, F/O=1, typical wire length)
|
|
Output buffer
|
1.30 ns (supply voltage: 5.0 V, IOL=9 mA, CL=15 pF) 2.02 ns (supply voltage: 3.3 V, IOL=9 mA, CL=15 pF)
|
|
Maximum operating frequency
|
5 V operation: 60 MHz 3.3 V operation: 33 MHz 3.0 V operation: 25 MHz (depend on the circuit configuration)
|
|
Output drive capacity
|
IOL=3, 6, 9, 12, 18, 24 mA
|
|
Operating ambient temperature
|
TA=-40 to 85°C
|
|
I/O buffer
|
CMOS level, TTL level (no output), oscillation block (MHz band)
|
|
Memory macro
|
Asynchronous high-density single-/dual-port RAM
|
|
Mega macros
|
-Programmable DMA controller -Serial control unit -Programmable timer counter -Parallel interface unit -Interrupt control unit -UART
|
|
Test related
|
SCAN, BSCAN
|
|
Other macros
|
CTS
|
|