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Master / Package Lineup: Dual power supply


Although customers can select their optimum package from among the many package types listed in this table, some selections may involve implementation issues and so customers should contact NEC Electronics for further information when making a selection.




3-metal layer (1/4)

Please attend to singnal pin because all masters do not necessarily keep the same.


Master


µPD65421 µPD65422 µPD65473 µPD65474
Density Number of raw gates 14,942 37,338 76,720 103,032
Number of usable gates*1 9,712 24,269 46,032 61,819
I/O pads 76 116 172 196

Note(*)

  1. Cell usability : 60% to 65% (variable, depending on the pin pairs and cell based IC Macro occuppied cells (preliminary))

Package

PKG Pin Number of
available pins
Pitch Body
(mm)
µPD65421 µPD65422 µPD65473 µPD65474
SSOP 20 17 0.65 6.65x6.1
30 27 0.65 9.85x
6.1
QFP
(FP)
100 88 0.5 14x14
120 106 0.5 20x20
144 128 0.5 20x20
160 136 0.5 24x24
176 152 0.5 24x24
208 180 0.5 28x28
240 204 0.5 32x32
TQFP 48*1
48*2,3
45 0.5 7x7
64*1
64*2,3
60 0.5 10x10
80 68 0.5 12x12
100*1,2
100*3
88 0.5 14x14
120*1,2
120*3
106 0.4 14x14
LQFP 44 41 0.8 10x10
100 88 0.5 14x14
144*1,2
144*3
128 0.5 20x20
160 136 0.5 24x24
176 152 0.5 24x24
216 190 0.4 24x24
PBGA 256 223 1.27 27x27
256 208 1.0 17x17
272 219 1.27 27x27
313 244 1.27
(Staggered)
35x35
FPBGA
*4
48 41 0.5 4.38x4.38
61 48 0.5 5x5
65 48 0.5 6x6
80 68 0.8 9x9
97 84 0.5 6x6
108 96 0.8 11x11
144 128 0.8 13x13
144 128 0.5 7x7
160 138 0.8 13x13
161 138 0.65 10x10
176 154 0.8 15x15
208 180 0.8 15x15
240 200 0.8 19x19
249 204 0.65 13x13
QFN 28 25 0.5 5x5
36 33 0.5 6x6
48 45 0.5 7x7

: Combination available

Note(*)

  1. Outline drawings for ES (Engineering Sample).
  2. Outline drawings for CS (Commercial Sample).
  3. Outline drawings for MP (Mass Production).
  4. JEDEC recommended soldering conditions Up to 208 pins = LEVEL3, 240 pins or more = LEVEL4


3-metal layer (2/4)

Please attend to singnal pin because all masters do not necessarily keep the same.


Master


µPD65475 µPD65476 µPD65478
Density Number of raw gates 128,872 207,000 314,104
Number of usable gates*1 77,323 124,200 188,462
I/O pads 216 268 324

Note(*)

  1. Cell usability : 60% (variable, depending on the pin pairs and cell based IC Macro occuppied cells (preliminary))

Package

PKG Pin Number of
available pins
Pitch Body
(mm)
µPD65475 µPD65476 µPD65478
SSOP 20 17 0.65 6.65x6.1
30 27 0.65 9.85x
6.1
QFP
(FP)
100 88 0.5 14x14
120 106 0.5 20x20
144 128 0.5 20x20
160 136 0.5 24x24
176 152 0.5 24x24
208 180 0.5 28x28
240 204 0.5 32x32
TQFP 48*1
48*2,3
45 0.5 7x7
64*1
64*2,3
60 0.5 10x10
80 68 0.5 12x12
100*1,2
100*3
88 0.5 14x14
120*1,2
120*3
106 0.4 14x14
LQFP 44 41 0.8 10x10
100 88 0.5 14x14
144*1,2
144*3
128 0.5 20x20
160 136 0.5 24x24
176 152 0.5 24x24
216 190 0.4 24x24
PBGA 256 223 1.27 27x27
256 208 1.0 17x17
272 219 1.27 27x27
313 244 1.27
(Staggered)
35x35
FPBGA
*4
48 41 0.5 4.38x4.38
61 48 0.5 5x5
65 48 0.5 6x6
80 68 0.8 9x9
97 84 0.5 6x6
108 96 0.8 11x11
144 128 0.8 13x13
144 128 0.5 7x7
160 138 0.8 13x13
161 138 0.65 10x10
176 154 0.8 15x15
208 180 0.8 15x15
240 200 0.8 19x19
249 204 0.65 13x13
QFN 28 25 0.5 5x5
36 33 0.5 6x6
48 45 0.5 7x7

: Combination available

Note(*)

  1. Outline drawings for ES (Engineering Sample).
  2. Outline drawings for CS (Commercial Sample).
  3. Outline drawings for MP (Mass Production).
  4. JEDEC recommended soldering conditions Up to 208 pins = LEVEL3, 240 pins or more = LEVEL4


3-metal layer (3/4)

Please attend to singnal pin because all masters do not necessarily keep the same.


Master


µPD65479 µPD65481 µPD65484
Density Number of raw gates 440,832 592,020 840,768
Number of usable gates*1 220,416 296,010 420,384
I/O pads 380 436 516

Note(*)

  1. Cell usability : 45% to 50% (variable, depending on the pin pairs and cell based IC Macro occuppied cells (preliminary))

Package

PKG Pin Number of
available pins
Pitch Body
(mm)
µPD65479 µPD65481 µPD65484
QFP
(FP)
100 88 0.5 14x14
144 128 0.5 20x20
160 136 0.5 24x24
176 152 0.5 24x24
208 180 0.5 28x28
240 204 0.5 32x32
304 252 0.5 40x40
TQFP 100*1,2
100*3
88 0.5 14x14
120*1,2
120*3
106 0.4 14x14
LQFP 100 88 0.5 14x14
144*1,2
144*3
128 0.5 20x20
PBGA 256 223 1.27 27x27
256 208 1.0 17x17
272 223 1.27 27x27
313 244 1.27
(Staggered)
35x35
352 292 1.27 35x35
FPBGA
*4
144 128 0.8 13x13
160 138 0.8 13x13
161 138 0.65 10x10
176 154 0.8 15x15
208 180 0.8 15x15
240 200 0.8 19x19
304 236 0.8 19x19
393 320 0.65 16x16

: Combination available

Note(*)

  1. Outline drawings for ES (Engineering Sample).
  2. Outline drawings for CS (Commercial Sample).
  3. Outline drawings for MP (Mass Production).
  4. JEDEC recommended soldering conditions Up to 208 pins = LEVEL3, 240 pins or more = LEVEL4


3-metal layer (4/4)

Please attend to singnal pin because all masters do not necessarily keep the same.


Master


µPD65486 µPD65488
Density Number of raw gates 1,104,432 1,626,628
Number of usable gates*1 552,216 731,982
I/O pads 588 708

Note(*)

  1. Cell usability : 45% to 50% (variable, depending on the pin pairs and cell based IC Macro occuppied cells (preliminary))

Package

PKG Pin Number of
available pins
Pitch Body
(mm)
µPD65486 µPD65488
QFP
(FP)
100 88 0.5 14x14
144 128 0.5 20x20
160 136 0.5 24x24
176 152 0.5 24x24
208 180 0.5 28x28
240 204 0.5 32x32
304 252 0.5 40x40
TQFP 100*1,2
100*3
88 0.5 14x14
120*1,2
120*3
106 0.4 14x14
LQFP 100 88 0.5 14x14
144*1,2
144*3
128 0.5 20x20
PBGA 256 223 1.27 27x27
256 208 1.0 17x17
272 223 1.27 27x27
313 244 1.27
(Staggered)
35x35
352 292 1.27 35x35
FPBGA
*4
144 128 0.8 13x13
160 138 0.8 13x13
161 138 0.65 10x10
176 154 0.8 15x15
208 180 0.8 15x15
240 200 0.8 19x19
304 236 0.8 19x19
393 320 0.65 16x16

: Combination available

Note(*)

  1. Outline drawings for ES (Engineering Sample).
  2. Outline drawings for CS (Commercial Sample).
  3. Outline drawings for MP (Mass Production).
  4. JEDEC recommended soldering conditions Up to 208 pins = LEVEL3, 240 pins or more = LEVEL4


4-metal layer (1/2)

Please attend to singnal pin because all masters do not necessarily keep the same.


Master


µPD65491 µPD65494 µPD65496 µPD65498
Density Number of raw gates 592,020 840,768 1,104,432 1,626,628
Number of usable gates*1 355,212 504,460 662,659 894,645
I/O pads 436 516 588 708

Note(*)

  1. Cell usability : 55% to 60% (variable, depending on the pin pairs and cell based IC Macro occuppied cells (preliminary))

Package

PKG Pin Number of
available pins
Pitch Body
(mm)
µPD65491 µPD65494 µPD65496 µPD65498
QFP (FP) 100 88 0.5 14x14
144 128 0.5 20x20
160 136 0.5 24x24
176 152 0.5 24x24
208 180 0.5 28x28
240 204 0.5 32x32
304 252 0.5 40x40
LQFP 100 88 0.5 14x14
144*1,2
144*3
128 0.5 20x20
PBGA 256 223 1.27 27x27
272 223 1.27 27x27
313 244 1.27
(Staggered)
35x35
352 292 1.27 35x35
FPBGA
*4
144 128 0.8 13x13
160 138 0.8 13x13
161 138 0.65 10x10
176 154 0.8 15x15
208 180 0.8 15x15
240 200 0.8 19x19
304 236 0.8 19x19
393 320 0.65 16x16

: Combination available

Note(*)

  1. Outline drawings for ES (Engineering Sample).
  2. Outline drawings for CS (Commercial Sample).
  3. Outline drawings for MP (Mass Production).
  4. JEDEC recommended soldering conditions Up to 208 pins = LEVEL3, 240 pins or more = LEVEL4


4-metal layer (2/2)

Please attend to singnal pin because all masters do not necessarily keep the same.


Master


µPD65499 µPD65400 µPD65401
Density Number of raw gates 1,906,800 2,203,360 2,521,344
Number of usable gates*1 1,048,740 1,211,848 1,386,739
I/O pads 764 820 876

Note(*)

  1. Cell usability : 55% to 60% (variable, depending on the pin pairs and cell based IC Macro occuppied cells (preliminary))

Package

PKG Pin Number of
available pins
Pitch Body
(mm)
µPD65499 µPD65400 µPD65401
QFP (FP) 100 88 0.5 14x14
144 128 0.5 20x20
160 136 0.5 24x24
176 152 0.5 24x24
208 180 0.5 28x28
240 204 0.5 32x32
304 252 0.5 40x40
LQFP 100 88 0.5 14x14
144*1,2
144*3
128 0.5 20x20
PBGA 256 223 1.27 27x27
272 223 1.27 27x27
313 244 1.27
(Staggered)
35x35
352 292 1.27 35x35
FPBGA
*4
144 128 0.8 13x13
160 138 0.8 13x13
161 138 0.65 10x10
176 154 0.8 15x15
208 180 0.8 15x15
240 200 0.8 19x19
304 236 0.8 19x19
393 320 0.65 16x16

: Combination available

Note(*)

  1. Outline drawings for ES (Engineering Sample).
  2. Outline drawings for CS (Commercial Sample).
  3. Outline drawings for MP (Mass Production).
  4. JEDEC recommended soldering conditions Up to 208 pins = LEVEL3, 240 pins or more = LEVEL4