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Master / Package Lineup (3-metal layer / 4-metal layer)


Although customers can select their optimum package from among the many package types listed in this table, some selections may involve implementation issues and so customers should contact NEC Electronics for further information when making a selection.




3-metal layer (1/4)

Please attend to singnal pin because all masters do not necessarily keep the same.


Master


µPD65941 µPD65942 µPD65943 µPD65944
Density Number of raw gates 14,942 37,338 75,740 100,602
Number of usable gates*1 11,207 28,004 53,018 70,421
I/O pads 76 116 172 196

Note(*)

  1. Cell usability: 70% to 75% (variable, depending on the number of pin-pairs)

Package

PKG Pin Number of
available pins
Pitch Body
(mm)
µPD65941 µPD65942 µPD65943 µPD65944
SSOP 20 18 0.65 6.65x6.1
30 28 0.65 9.85x6.1
QFP
(FP)
100 92 0.5 14x14
120 110 0.5 20x20
144 132 0.5 20x20
160 144 0.5 24x24
176 160 0.5 24x24
208 188 0.5 28x28
240 212 0.5 32x32
TQFP 48*1
48*2,3
46 0.5 7x7
64*1
64*2,3
61 0.5 10x10
80 72 0.5 12x12
100*1,2
100*3
92 0.5 14x14
120*1,2
120*3
110 0.4 14x14
LQFP 44 42 0.8 10x10
100 92 0.5 14x14
144*1,2
144*3
132 0.5 20x20
160 144 0.5 24x24
176 160 0.5 24x24
216 198 0.4 24x24
PBGA 256 231 1.27 27x27
256 224 1.0 17x17
272 231 1.27 27x27
313 256 1.27
(Staggered)
35x35
FPBGA
*4
48 43 0.5 4.38x4.38
61 52 0.5 5x5
65 52 0.5 6x6
80 72 0.8 9x9
97 88 0.5 6x6
108 100 0.8 11x11
144 132 0.8 13x13
144 132 0.5 7x7
160 144 0.8 13x13
161 144 0.65 10x10
176 160 0.8 15x15
208 188 0.8 15x15
240 212 0.8 19x19
249 212 0.65 13x13
QFN 28 26 0.5 5x5
36 34 0.5 6x6
48 46 0.5 7x7

: Combination available

Note(*)

  1. Outline drawings for ES (Engineering Sample).
  2. Outline drawings for CS (Commercial Sample).
  3. Outline drawings for MP (Mass Production).
  4. JEDEC recommended soldering conditions Up to 208 pins = LEVEL3, 240 pins or more = LEVEL4


3-metal layer (2/4)

Please attend to singnal pin because all masters do not necessarily keep the same.


Master


µPD65945 µPD65946 µPD65948
Density Number of raw gates 128,338 202,630 312,684
Number of usable gates*1 89,836 141,841 218,879
I/O pads 216 268 324

Note(*)

  1. Cell usability: 70% to 75% (variable, depending on the number of pin-pairs)

Package

PKG Pin Number of
available pins
Pitch Body
(mm)
µPD65945 µPD65946 µPD65948
SSOP 20 18 0.65 6.65x6.1
30 28 0.65 9.85x6.1
QFP
(FP)
100 92 0.5 14x14
120 110 0.5 20x20
144 132 0.5 20x20
160 144 0.5 24x24
176 160 0.5 24x24
208 188 0.5 28x28
240 212 0.5 32x32
TQFP 48*1
48*2,3
46 0.5 7x7
64*1
64*2,3
61 0.5 10x10
80 72 0.5 12x12
100*1,2
100*3
92 0.5 14x14
120*1,2
120*3
110 0.4 14x14
LQFP 44 42 0.8 10x10
100 92 0.5 14x14
144*1,2
144*3
132 0.5 20x20
160 144 0.5 24x24
176 160 0.5 24x24
216 198 0.4 24x24
PBGA 256 231 1.27 27x27
256 224 1.0 17x17
272 231 1.27 27x27
313 256 1.27
(Staggered)
35x35
FPBGA
*4
48 43 0.5 4.38x4.38
61 52 0.5 5x5
65 52 0.5 6x6
80 72 0.8 9x9
97 88 0.5 6x6
108 100 0.8 11x11
144 132 0.8 13x13
144 132 0.5 7x7
160 144 0.8 13x13
161 144 0.65 10x10
176 160 0.8 15x15
208 188 0.8 15x15
240 212 0.8 19x19
249 212 0.65 13x13
QFN 28 26 0.5 5x5
36 34 0.5 6x6
48 46 0.5 7x7

: Combination available

Note(*)

  1. Outline drawings for ES (Engineering Sample).
  2. Outline drawings for CS (Commercial Sample).
  3. Outline drawings for MP (Mass Production).
  4. JEDEC recommended soldering conditions Up to 208 pins = LEVEL3, 240 pins or more = LEVEL4


3-metal layer (3/4)

Please attend to singnal pin because all masters do not necessarily keep the same.


Master


µPD65949 µPD65951 µPD65954
Density Number of raw gates 437,136 585,390 835,664
Number of usable gates*1 262,281 321,964 459,615
I/O pads 380 436 516

Note(*)

  1. Cell usability: 50% to 60% (variable, depending on the number of pin-pairs)

Package

PKG Pin Number of
available pins
Pitch Body
(mm)
µPD65949 µPD65951 µPD65954
QFP
(FP)
100 92 0.5 14x14
144 132 0.5 20x20
160 144 0.5 24x24
176 160 0.5 24x24
208 188 0.5 28x28
240 212 0.5 32x32
304 256 0.5 40x40
TQFP 100*1,2
100*3
92 0.5 14x14
120*1,2
120*3
110 0.4 14x14
LQFP 100 92 0.5 14x14
144*1,2
144*3
132 0.5 20x20
PBGA 256 231 1.27 27x27
256 224 1.0 17x17
272 231 1.27 27x27
313 256 1.27
(Staggered)
35x35
352 304 1.27 35x35
676 504 1.00 27x27
FPBGA
*4
144 132 0.8 13x13
160 144 0.8 13x13
161 144 0.65 10x10
176 160 0.8 15x15
208 188 0.8 15x15
240 212 0.8 19x19
304 256 0.8 19x19
393 336 0.65 16x16

: Combination available

Note(*)

  1. Outline drawings for ES (Engineering Sample).
  2. Outline drawings for CS (Commercial Sample).
  3. Outline drawings for MP (Mass Production).
  4. JEDEC recommended soldering conditions Up to 208 pins = LEVEL3, 240 pins or more = LEVEL4


3-metal layer (4/4)

Please attend to singnal pin because all masters do not necessarily keep the same.


Master


µPD65956 µPD65958
Density Number of raw gates 1,096,452 1,615,646
Number of usable gates*1 603,048 807,823
I/O pads 588 708

Note(*)

  1. Cell usability: 50% to 60% (variable, depending on the number of pin-pairs)

Package

PKG Pin Number of
available pins
Pitch Body
(mm)
µPD65956 µPD65958
QFP
(FP)
100 92 0.5 14x14
144 132 0.5 20x20
160 144 0.5 24x24
176 160 0.5 24x24
208 188 0.5 28x28
240 212 0.5 32x32
304 256 0.5 40x40
TQFP 100*1,2
100*3
92 0.5 14x14
120*1,2
120*3
110 0.4 14x14
LQFP 100 92 0.5 14x14
144*1,2
144*3
132 0.5 20x20
PBGA 256 231 1.27 27x27
256 224 1.0 17x17
272 231 1.27 27x27
313 256 1.27
(Staggered)
35x35
352 304 1.27 35x35
676 504 1.00 27x27
FPBGA
*4
144 132 0.8 13x13
160 144 0.8 13x13
161 144 0.65 10x10
176 160 0.8 15x15
208 188 0.8 15x15
240 212 0.8 19x19
304 256 0.8 19x19
393 336 0.65 16x16

: Combination available

Note(*)

  1. Outline drawings for ES (Engineering Sample).
  2. Outline drawings for CS (Commercial Sample).
  3. Outline drawings for MP (Mass Production).
  4. JEDEC recommended soldering conditions Up to 208 pins = LEVEL3, 240 pins or more = LEVEL4


4-metal layer (1/2)

Please attend to singnal pin because all masters do not necessarily keep the same.


Master


µPD65961 µPD65964 µPD65966 µPD65968
Density Number of raw gates 585,390 835,664 1,096,452 1,615,646
Number of usable gates*1 380,503 543,181 712,693 969,387
I/O pads 436 516 588 708

Note(*)

  1. Cell usability: 60% to 65% (variable, depending on the number of pin-pairs)

Package

PKG Pin Number of
available pins
Pitch Body
(mm)
µPD65961 µPD65964 µPD65966 µPD65968
QFP
(FP)
100 92 0.5 14x14
144 132 0.5 20x20
160 144 0.5 24x24
176 160 0.5 24x24
208 188 0.5 28x28
240 212 0.5 32x32
304 256 0.5 40x40
LQFP 100 92 0.5 14x14
144*1,2
144*3
132 0.5 20x20
PBGA 256 231 1.27 27x27
272 231 1.27 27x27
313 256 1.27
(Staggered)
35x35
352 304 1.27 35x35
676 504 1.00 27x27
FPBGA
*4
144 132 0.8 13x13
160 144 0.8 13x13
161 144 0.65 10x10
176 160 0.8 15x15
208 188 0.8 15x15
240 212 0.8 19x19
304 256 0.8 19x19
393 336 0.65 16x16

: Combination available

Note(*)

  1. Outline drawings for ES (Engineering Sample).
  2. Outline drawings for CS (Commercial Sample).
  3. Outline drawings for MP (Mass Production).
  4. JEDEC recommended soldering conditions Up to 208 pins = LEVEL3, 240 pins or more = LEVEL4


4-metal layer (2/2)

Please attend to singnal pin because all masters do not necessarily keep the same.


Master


µPD65969 µPD65970 µPD65971
Density Number of raw gates 1,904,700 2,196,592 2,509,284
Number of usable gates*1 1,142,820 1,317,955 1,505,570
I/O pads 764 820 876

Note(*)

  1. Cell usability: 60% to 65% (variable, depending on the number of pin-pairs)

Package

PKG Pin Number of
available pins
Pitch Body
(mm)
µPD65969 µPD65970 µPD65971
QFP
(FP)
100 92 0.5 14x14
144 132 0.5 20x20
160 144 0.5 24x24
176 160 0.5 24x24
208 188 0.5 28x28
240 212 0.5 32x32
304 256 0.5 40x40
LQFP 100 92 0.5 14x14
144*1,2
144*3
132 0.5 20x20
PBGA 256 231 1.27 27x27
272 231 1.27 27x27
313 256 1.27
(Staggered)
35x35
352 304 1.27 35x35
FPBGA
*4
144 132 0.8 13x13
160 144 0.8 13x13
161 144 0.65 10x10
176 160 0.8 15x15
208 188 0.8 15x15
240 212 0.8 19x19
304 256 0.8 19x19
393 336 0.65 16x16

: Combination available

Note(*)

  1. Outline drawings for ES (Engineering Sample).
  2. Outline drawings for CS (Commercial Sample).
  3. Outline drawings for MP (Mass Production).
  4. JEDEC recommended soldering conditions Up to 208 pins = LEVEL3, 240 pins or more = LEVEL4