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Products > ASIC > Gate Arrays and Embedded Arrays > Product Lineup > CMOS-12M Series >

CMOS-12M Series


  • CMOS-N5 5V system
  • CMOS-9HD 3.3V system
  • EA-9HD 3.3V system
  • CMOS-12M 1.5V system

Product OverviewMaster/Package Lineup

SOG type CMOS-12M Series

Features Application Application Examples Specification Master/Package Lineup


Features

System Clock Frequency: Max. 250 MHz

LVDS channel: Approx. doubled from CMOS-12M

Few Gates, No Embedded RAM

Four masters are available with 62K to 499K usable gates. Compiled RAM is used for the memory.

Compact Packages

Available in various packages, including 97-pin FPBGA (6×6 mm) and 144-pin FPBGA (7×7 mm).


Application

  • Commercial and industrial bridge ICs requiring the 250 MHz transmission clock
    • High-speed transmissions, i.e. for LVDS
    • Level conversion circuits for high-speed signals (i.e. 3.3 V ⇔ 2.5 V, 1.8 V)
  • Replacing existing Gate Arrays for compatibility with high-speed transmissions
  • The most inexpensive Gate Arrays for high-speed transmission circuits with small circuit size (499K gates or less) and small memory capacity

Application Examples


Specification

Item Existing CMOS-12M SOG type CMOS-12M
Technology 150nm (Technology-Node)
Power supply voltage (Inside)1.5V±10%,(Outside)3.3V/2.5V/1.8V/1.5V
Delay time 62ps(2-input NAND,F/O=1,typical length)
Number of usable gates 151K - 2M gates
(RAM:96K-2.7Mbits) 		62K - 499K gates
System clock frequency (Max.) 200MHz 250MHz
Power consumption(VDD=1.5V) 21.6nW/MHz/gate(Operation rate=0.35)
Macros Embedded RAM Yes No
SRAM 1port, 2port, Dualport 1port, 2port
APLL Phase-shift-type PLL
SSCG 		New phase-shift-type PLL
SSCG
DLL SlaveDLL -
Package LQFP/QFP(100-208pin)
FPBGA(108-208pin)
PBGA(256-676pin) 		LQFP(100-144pin),
0.5mmpitch FPBGA(97-144pin)
FPBGA(108-208pin)


Master/Package Lineup

97-pin FPBGA (6×6 mm) and 144-pin FPBGA (7×7 mm) will be added to the lineup.
CMOS-12M series is currently under development. The specifications provided below may not be up-to-date. Contact NEC Electronics for the latest information.


Master Lineup


µPD66211 µPD66212 µPD66213 µPD66214
Number of cell *1 104K 242K 502K 831K
Number of usable gates 62K 144K 301K 499K
Number of APLL 2 2 2 2
LVDS Number of channel*2 16 28 39 51

Note(*)


  1. The number of mounted cells is calculated by a 2-input NAND operation (1 cell = 1 gate).
  2. Number of physical channels available. May vary depending on added VG.

Package Lineup


Type Pin Pitch (mm) Body size (mm) µPD66211 µPD66212 µPD66213 µPD66214
LQFP 100 0.5 14 × 14 Ο Ο Ο Ο
144 0.5 20 × 20 - Ο Ο Ο
FPBGA 97 0.5 6 × 6 Ο Ο Ο -
144 0.5 7 × 7 - Ο Ο Ο
108 0.8 11 × 11 Ο Ο Ο Ο
160 0.8 13 × 13 - Ο Ο Ο
208 0.8 15 × 15 - - Ο Ο
PBGA 256 1.0 17 × 17 - - - Ο


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