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CMOS-12M Series



  • CMOS-N5 5V system
  • CMOS-9HD 3.3V system
  • EA-9HD 3.3V system
  • CMOS-12M 1.5V system

Product OverviewMaster/Package Lineup

CMOS-12M Series Product Overview

The CMOS-12M series represents a link between Gate Arrays technologies and deep-submicron ASICs. This Gate Array series is based on a 150 nm CMOS process, making use of five or six metal layers for optimum routing. Another key feature of CMOS-12M is the availability of embedded high-density, dual-port SRAM blocks.




Expansion of the CMOS-12M Series

SOG type products have been released to expand the lineup of the high-speed version of CMOS-12M.


Special Features

  • 150nm node length, 1.5V supply voltage
  • Sea-of-gates architecture with embedded high-density SRAM blocks
  • Ambient operating temperature from -40 to +85°C (industrial)
  • Low unit cost and low NRE cost

Application

  • Any equipment that requires large-scale memory
  • Any equipment that requires high-speed operation
  • Any equipment whose power consumption should be reduced
  • Any equipment that should be downsized
  • Any equipment whose cost should be reduced

Application Examples


Specification

Item Specification
Process 0.15 µm CMOS process
Number of usable gates 62K - 2M gates
Package 100/144 LQFP, 208 QFP(FP), 97/144/108/160/208 FPBGA,
256/324/449/676 PBGA
Supply voltage Internal:1.5±0.15 V
External:3.3 V, 2.5 V, 1.8 V, 1.5 V
Power consumption
(VDD=1.5 V)
21.6 nW/MHz/gate (Operation rate=0.35)
Delay time 62 ps (2-input NAND, F/O=1, typical wire length)
System clock frequency 200 MHz
Output drive capacity IOLH=3, 6, 9, 12 mA
Operating ambient temperature TA=-40 to 85°C
I/O interface 3.3V CMOS, LVTTL, LVPECL, 2.5V CMOS, 2.5V LVDS, 1.8V CMOS,
SSTL2, SSTL3, 2.5V LVPECL, 3.3V PCI, HSTL, GTL+
Memory macro Synchronous 1-port or 2-port compiled RAM, Embedded RAM
Mega macros -UART
Embedded macros -SRAM: Synchronous dual-port compiled RAM
-APLL: Phase-shift type, SSCG type
-Slave DLL: For high-speed SDRAM interface
Embedded test-related SCAN, BSCAN, BIST



Inquiry Concerning Gate Arrays




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