CMOS-12M Series
CMOS-12M Series Product Overview
The CMOS-12M series represents a link between Gate Arrays technologies and deep-submicron ASICs. This Gate Array series is based on a 150 nm CMOS process, making use of five or six metal layers for optimum routing. Another key feature of CMOS-12M is the availability of embedded high-density, dual-port SRAM blocks.
Expansion of the CMOS-12M Series
SOG type products have been released to expand the lineup of the high-speed version of CMOS-12M.
Special Features
- 150nm node length, 1.5V supply voltage
- Sea-of-gates architecture with embedded high-density SRAM blocks
- Ambient operating temperature from -40 to +85°C (industrial)
- Low unit cost and low NRE cost
Application
- Any equipment that requires large-scale memory
- Any equipment that requires high-speed operation
- Any equipment whose power consumption should be reduced
- Any equipment that should be downsized
- Any equipment whose cost should be reduced
Application Examples
Specification
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Item
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Specification
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Process
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0.15 µm CMOS process
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Number of usable gates
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62K - 2M gates
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Package
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100/144 LQFP, 208 QFP(FP), 97/144/108/160/208 FPBGA, 256/324/449/676 PBGA
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Supply voltage
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Internal:1.5±0.15 V External:3.3 V, 2.5 V, 1.8 V, 1.5 V
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Power consumption (VDD=1.5 V)
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21.6 nW/MHz/gate (Operation rate=0.35)
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Delay time
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62 ps (2-input NAND, F/O=1, typical wire length)
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System clock frequency
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200 MHz
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Output drive capacity
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IOLH=3, 6, 9, 12 mA
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Operating ambient temperature
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TA=-40 to 85°C
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I/O interface
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3.3V CMOS, LVTTL, LVPECL, 2.5V CMOS, 2.5V LVDS, 1.8V CMOS, SSTL2, SSTL3, 2.5V LVPECL, 3.3V PCI, HSTL, GTL+
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Memory macro
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Synchronous 1-port or 2-port compiled RAM, Embedded RAM
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Mega macros
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-UART
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Embedded macros
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-SRAM: Synchronous dual-port compiled RAM -APLL: Phase-shift type, SSCG type -Slave DLL: For high-speed SDRAM interface
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Embedded test-related
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SCAN, BSCAN, BIST
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Inquiry Concerning Gate Arrays