Beginning of this page
Jump to main content

Please note that JavaScript and style sheet are used in this website,
Due to unadaptability of the style sheet with the browser used in your computer, pages may not look as original.
Even in such a case, however, the contents can be used safely.

Products > ASIC > Gata Array and Embedded Array > Product Lineup >

CMOS-12M Series


The CMOS-12M series represents a link between gate array technologies and deep-submicron ASICs. This gate array series is based on a 150 nm CMOS process, making use of five or six metal layers for optimum routing. Another key feature of CMOS-12M is the availability of embedded high-density, dual-port SRAM blocks.


Special Features

  • 150 nm node length, 1.5V supply voltage
  • Sea-of-gates architecture with embedded high-density SRAM blocks
  • Ambient operating temperature from -40 to +85°C (industrial)
  • Low unit cost and low NRE cost

Application

  • Any equipment that requires large-scale memory
  • Any equipment that requires high-speed operation
  • Any equipment whose power consumption should be reduced
  • Any equipment that should be downsized
  • Any equipment whose cost should be reduced


Specification

Item Specification
Process 0.15 µm CMOS process
Number of usable gates 125,000 to 2,000,000 gates
Package 100/144 LQFP, 208 QFP(FP), 108/160/208 FPBGA,
256/324/449/676 PBGA, 352/500/576/672/756 ABGA
Supply voltage Internal:1.5±0.15 V
External:3.3 V, 2.5 V, 1.8 V, 1.5 V (1.5V and 1.8V are under development)
Power consumption
(VDD=1.5 V) 		19.6 nW/MHz/gate (Operation rate=0.35)
Delay time 62 ps (2-input NAND, F/O=1, typical wire length)
System clock frequency 200 MHz
Output drive capacity IOLH=3, 6, 9, 12 mA
Operating ambient temperature TA=-40 to 85°C
I/O interface 3.3V CMOS, LVTTL, LVPECL, 2.5V CMOS, 2.5V LVDS,
SSTL2, SSTL3, 2.5V LVPECL, 3.3V PCI, HSTL, GTL+
Memory macro Synchronous 1-port or 2-port compiled RAM, Embedded RAM
Mega macros -UART
-PCI controller
-DDR controller
Embedded macros -SRAM: Synchronous dual-port compiled RAM
-APLL: Phase-shift type, SSCG type
-Slave DLL: For high-speed SDRAM interface
Embedded test-related SCAN, BSCAN, BIST


Interface Information

I/O types Frequency (MHz) VDDQ (V)
LVTTL 133 -
2.5 V CMOS 133 2.5
1.8 V CMOS 133 1.8
SSTL3 300 -
SSTL2 300 2.5
1.5 V HSTL 266 1.5
1.8 V HSTL 266 1.8
LVPECL 300 -
2.5 V PECL 300 2.5
2.5 V LVDS 333 2.5
2.5 V RSDS 200 2.5
PCI 66 -
PCI-X (mode1) 133 -