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Master / Package Lineup: Single power supply


Although customers can select their optimum package from among the many package types listed in this table, some selections may involve implementation issues and so customers should contact NEC Electronics for further information when making a selection.




Single power supply (1/5)

Please attend to singnal pin because all masters do not necessarily keep the same.


Master


3-metal master µPD65318 µPD65319
Density Number of raw gates 10,452 32,490
Number of usable gates*1 3-metal layer 6,793 21,118
I/O pads 60 84

Note(*)

  1. Cell usability: 60% to 70% (variable, depending on the number of pin-pairs)

Package

PKG Pin Number of
available pins
Pitch Body
(mm)
µPD65318 µPD65319
TQFP 48*1
48*2,3
46 0.5 7x7
64*1
64*2,3
61 0.5 10x10
80 72 0.5 12x12
LQFP 44 42 0.8 10x10
FPBGA
*4
48 43 0.5 4.38x4.38
61 52 0.5 5x5
85 Planning Planning Planning
QFN 28 26 0.5 5x5
36 34 0.5 6x6
48 46 0.5 7x7

: Combination available

Note(*)

  1. Outline drawings for ES (Engineering Sample).
  2. Outline drawings for CS (Commercial Sample).
  3. Outline drawings for MP (Mass Production).
  4. JEDEC recommended soldering conditions Up to 208 pins = LEVEL3, 240 pins or more = LEVEL4


Single power supply (2/5)

Please attend to singnal pin because all masters do not necessarily keep the same.


Master


3-metal master
4-metal master
µPD65301
µPD65501
µPD65302
µPD65502
µPD65303
µPD65503
µPD65304
µPD65504
Density Number of raw gates 58,682 128,338 192,058 299,472
Number of usable gates*1 3-metal layer 38,143 83,420 124,837 194,657
4-metal layer 41,077 89,837 134,441 209,630
I/O pads 132 188 228 284

Note(*)

  1. Cell usability: 60% to 70% (variable, depending on the number of pin-pairs)

Package

PKG Pin Number of
available pins
Pitch Body
(mm)
µPD65301
µPD65501
µPD65302
µPD65502
µPD65303
µPD65503
µPD65304
µPD65504
QFP(FP) 160 144 0.5 24x24
208 188 0.5 28x28
240 212 0.5 32x32
304 256 0.5 40x40
TQFP 48*1
48*2,3
46 0.5 7x7
64*1
64*2,3
61 0.5 10x10
80 72 0.5 12x12
120*1,2
120*3
110 0.4 14x14
LQFP 44 42 0.8 10x10
100 92 0.5 14x14
144*1,2
144*3
132 0.5 20x20
FPBGA
*4
61 52 0.5 5x5
97 88 0.5 6x6
108 100 0.8 11x11
144 132 0.5 7x7
160 144 0.8 13x13
161 144 0.65 10x10
208 188 0.8 15x15
240 212 0.8 19x19
249 212 0.65 13x13
304 236 0.8 19x19
393 336 0.65 16x16
PBGA 256 231 1.27 27x27
313 256 1.27
(Staggered)
35x35
352 304 1.27 35x35
676 *5 1.0 27x27

: Combination available

Note(*)

  1. Outline drawings for ES (Engineering Sample).
  2. Outline drawings for CS (Commercial Sample).
  3. Outline drawings for MP (Mass Production).
  4. JEDEC recommended soldering conditions Up to 208 pins = LEVEL3, 240 pins or more = LEVEL4
  5. The number of signal pins differ depending on Master.


Single power supply (3/5)

Please attend to singnal pin because all masters do not necessarily keep the same.


Master


3-metal master
4-metal master
µPD65305
µPD65505
µPD65306
µPD65506
µPD65307
µPD65507
µPD65308
µPD65508
Density Number of raw gates 409,920 545,008 721,224 1,014,542
Number of usable gates*1 3-metal layer 245,952 299,754 396,673 557,998
4-metal layer 266,448 354,255 468,796 659,452
I/O pads 332 380 436 516

Note(*)

  1. Cell usability: 60% to 70% (variable, depending on the number of pin-pairs)

Package

PKG Pin Number of
available pins
Pitch Body
(mm)
µPD65305
µPD65505
µPD65306
µPD65506
µPD65307
µPD65507
µPD65308
µPD65508
QFP(FP) 160 144 0.5 24x24
208 188 0.5 28x28
240 212 0.5 32x32
304 256 0.5 40x40
TQFP 48*1
48*2,3
46 0.5 7x7
64*1
64*2,3
61 0.5 10x10
80 72 0.5 12x12
120*1,2
120*3
110 0.4 14x14
LQFP 44 42 0.8 10x10
100 92 0.5 14x14
144*1,2
144*3
132 0.5 20x20
FPBGA
*4
61 52 0.5 5x5
108 100 0.8 11x11
160 144 0.8 13x13
161 144 0.65 10x10
208 188 0.8 15x15
240 212 0.8 19x19
249 212 0.65 13x13
304 236 0.8 19x19
393 320 0.65 16x16
PBGA 256 231 1.27 27x27
313 256 1.27
(Staggered)
35x35
352 304 1.27 35x35
676 *5 1.0 27x27

: Combination available

Note(*)

  1. Outline drawings for ES (Engineering Sample).
  2. Outline drawings for CS (Commercial Sample).
  3. Outline drawings for MP (Mass Production).
  4. JEDEC recommended soldering conditions Up to 208 pins = LEVEL3, 240 pins or more = LEVEL4
  5. The number of signal pins differ depending on Master.


Single power supply (4/5)

Please attend to singnal pin because all masters do not necessarily keep the same.


Master


3-metal master
4-metal master
µPD65309
µPD65509
µPD65310
µPD65510
µPD65311
µPD65511
Density Number of raw gates 1,404,790 1,974,700 2,605,764
Number of usable gates*1 3-metal layer 702,395 987,350 1,302,882
4-metal layer 842,874 1,184,820 1,563,458
I/O pads 604 716 820

Note(*)

  1. Cell usability: 60% to 70% (variable, depending on the number of pin-pairs)

Package

PKG Pin Number of
available pins
Pitch Body
(mm)
µPD65309
µPD65509
µPD65310
µPD65510
µPD65311
µPD65511
QFP(FP) 160 144 0.5 24x24
208 188 0.5 28x28
240 212 0.5 32x32
304 256 0.5 40x40
TQFP 48*1
48*2,3
46 0.5 7x7
64*1
64*2,3
61 0.5 10x10
80 72 0.5 12x12
120*1,2
120*3
110 0.4 14x14
LQFP 44 42 0.8 10x10
100 92 0.5 14x14
144*1,2
144*3
132 0.5 20x20
FPBGA
*4
108 100 0.8 11x11
160 144 0.8 13x13
161 144 0.65 10x10
208 188 0.8 15x15
240 212 0.8 19x19
249 212 0.65 13x13
304 236 0.8 19x19
393 320 0.65 16x16
PBGA 256 231 1.27 27x27
313 256 1.27
(Staggered)
35x35
352 304 1.27 35x35
676 *5 1.0 27x27

: Combination available

Note(*)

  1. Outline drawings for ES (Engineering Sample).
  2. Outline drawings for CS (Commercial Sample).
  3. Outline drawings for MP (Mass Production).
  4. JEDEC recommended soldering conditions Up to 208 pins = LEVEL3, 240 pins or more = LEVEL4
  5. The number of signal pins differ depending on Master.


Single power supply (5/5)

Please attend to singnal pin because all masters do not necessarily keep the same.


Master


3-metal master
4-metal master
µPD65321
µPD65521
µPD65322
µPD65522
µPD65323
µPD65523
Density Number of raw gates 58,682 128,338 192,058
Number of usable gates*1 3-metal layer 38,143 83,420 124,837
4-metal layer 41,077 89,837 134,441
I/O pads 100 120 144

Note(*)

  1. Cell usability: 50% to 70% (variable, depending on the number of pin-pairs)

Package

PKG Pin Number of
available pins
Pitch Body
(mm)
µPD65321
µPD65521
µPD65322
µPD65522
µPD65323
µPD65523
TQFP 64*1
64*2,3
61 0.5 10x10
80 72 0.5 12x12
100*1,2
100*3
92 0.5 14x14
120*1,2
120*3
110 0.4 14x14
LQFP 100 92 0.5 14x14
144*1,2
144*3
132 0.5 20x20
FPBGA 97 88 0.5 6x6
144 132 0.5 7x7
QFN 28 26 0.5 5x5
36 34 0.5 6x6
48 46 0.5 7x7

: Combination available

Note(*)

  1. Outline drawings for ES (Engineering Sample).
  2. Outline drawings for CS (Commercial Sample).
  3. Outline drawings for MP (Mass Production).