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Japan
VR4181 VR4181A..(uPD30181 30181A)
Contents
FAQ-ID : VR4181-nnnn
| 0001 | Memory access |
|---|---|
| 0010 | A/D converter and D/A converter |
| 0002 | Touch panel interface |
| 0003 | USB controller |
| 0004 | Address mapping |
| 0005 | ISA bridge |
| 0006 | Clock |
| 0007 | Power modes |
| 0008 | Hazards |
| 0009 | Clock oscillator |
| 0011 | PC card controller |
Memory access
FAQ-ID : VR4181-0001Last Updated : 2006/03
- Q-1
-
Can wait control of the external ISA memory space be performed by hardware?
- A-1
-
The IORDY signal is valid even for the external ISA memory space.
- Q-2
-
The IORDY signal can be used for wait control.
Then, are the IORD# and IOWR# signals used to access the external ISA memory space?
- A-2
-
For read/write access, use the MEMRD# and MEMWR# signals.
- Q-3
-
What is the burst length during SDRAM access?
- A-3
-
The burst length is 8 words in the VR4181A.
This is the full page (full column length) burst length in the VR4181, specified via the BL (2:0) bits in the MODE_REG (0x0A000308) register.
For description of the full column length, see the documentation for the SDRAM being used.
- Q-4
-
Is the default pre-charge setting auto pre-charge?
- A-4
-
No, auto pre-charge is not supported.
- Q-5
-
What are the function of each bit in the VR4181's SDTIMINGREG register?
- A-5
-
The following setting functions are provided in the VR4181A's MEMCTRL and MEMTCTRL registers.
TRAS bit : Sets interval between issuing ACT and PRE commands TRC bit : Sets interval between issuing two ACT commands TRP bit : Sets interval between issuing PRE and ACT commands TRCD bit : Sets interval between issuing ACT and READ/WRITE commands 
- Q-6
-
Do settings have to be entered in the EDOMCYTREG register in order to use SDRAM?
- A-6
-
No, such settings are not required to use SDRAM.
- Q-7
-
What is "MEMC" that is mentioned in the description of the STOP_CLK bit in the VR4181's DRAMHIBCTL register?
- A-7
-
It refers to the memory controller.
- Q-8
-
Can ROM control be used for LCD control lines?
- A-8
-
The LCDCS signal can be used in the same way as the ROMCS signal.
An external LCD controller is selected via the GIU, the LCDCS space is assigned to the external ISA memory space, and memory access is used to access the LCD controller.
The interface for the external LCD controller can be used by setting the LCDGPEN bit in the LCDGPMODE register (to 1).
For this mode, be sure to replace the on-chip LCD controller's pin with the external LCD controller's interface signal as described below.
LCDCS# output is generated by the GIU's address decoder.
The address range can be set via the LCDGPMODE register as shown below.
(1) 0x1338 0000 to 0x133F FFFF (512 Kbytes)
(2) 0x133C 0000 to 0x133F FFFF (256 Kbytes)
(3) 0x133E 0000 to 0x133F FFFF (128 Kbytes)
(4) 0x130A 0000 to 0x130A FFFF (64 Kbytes: assuming the PC/AT TM address space)
Remark A 16-bit memory cycle is always used to access the external LCD controller's address space.
The ROM/system bus's control signals (MEMRD# and MEMWR#) can be used as read/write control signals.
For details, refer to "LCD Interface" in the User's Manual.
A/D converter and D/A converter
FAQ-ID : VR4181-0010Last Updated : 2006/03
- Q-1
-
Please explain the input and output impedance in the VR4181's A/D converter and D/A converter.
- A-1
-
These characteristics are the same as in the VR4181A. Please refer to the VR4181A's data sheet.
- Q-2
-
The User's Manual includes a drawing of the PIU's coordinate data scan, which shows that time division is used for the TP scan (DataScan) and AD scan (ADPScan).
Can't these two scan types be used at the same time?
- A-2
-
Such simultaneous processing is not possible because there is only one A/D converter.
However, since AD scans can be performed only via the timing required by the system, time division enables an AD scan to be performed during a TP operation.
Even if this interval is less than the time required for the conversion results, it is still regarded as simultaneous.
- Q-3
-
Can the selector for TP input and AD input be controlled by software?
- A-3
-
During normal operations, TP input is used and the state is changed to the ADPScan state when ADPSSTART in the PIUASNREG register is set to 1.
At that time, the input set via the TPPSCAN bit in the same register is selected.
Touch panel interface
FAQ-ID : VR4181-0002Last Updated : 2006/03
- Q-1
-
How can I scan the touch panel just by polling, without using any interrupts?
- A-1
-
Interrupt requests are reflected in the SYSTINTREG (0x0A00 0080) register, so poll this register. PIU interrupt requests are indicated by bit 5 (PIUINTR) in this register.
- Q-2
-
The User's Manual (Hardware) says that the resistance value between the touch panel interface unit (PIU)'s target pins (between X circuits or between Y circuits) is about 1 kΩ. What is the range for a controllable touch panel?
- A-2
-
The 1-kΩ resistance film value (resistance between edges) takes into account the output levels of the TPX0, TPX1, TPY0, and TPY1 pins.
Other reference values for resistance (current load) and output level are listed below.
Hypothetical resistance Load current High output level (MIN) Low output level (MAX) ---------------------------------------------------------------------------------------- 1 kΩ ± 3 mA 0.8 (VDD3) V 0.4 V 250 Ω ±12 mA 0.75(VDD3) V 0.7 V
- Q-3
-
Do any restrictions apply to the specifications for the electrostatic capacitance between the touch panel's two functional electrode films (X and Y)?
- A-3
-
The VR4181 (uPD30181) is designed for use with a quarter VGA size panel, and does not support larger sizes that have a larger capacitance.
This restriction does not apply to the VR4181A (uPD30181A) or the VR4121 (uPD30121).
USB controller
FAQ-ID : VR4181-0003Last Updated : 2006/03
- Q-1
-
Which versions of the USB standard do you support?
- A-1
-
We support the following USB versions.
- USB host controller (1 channel): USB Rev. 1.1, OHCI Rev. 1.0
- USB function controller (1 channel): USB Rev. 1.1
However, the VR4181 does not support USB.
Address mapping
FAQ-ID : VR4181-0004Last Updated : 2006/03
- Q-1
-
Even though the VR4181's ROM space is from 0x1FFFFFFF to 0x18000000, ROMCS0#, which is at the low end in ROM address mapping, starts from 0x1E000000. Why can't the range from 0x18000000 to 0x1dFFFFFF be used?
- A-1
-
The pins for ROMCS0# to ROMCS3# are mapped as shown in the ROM address mapping table, so 0x18000000 to 0x1dFFFFFF cannot be used.
ISA bridge
FAQ-ID : VR4181-0005Last Updated : 2006/03
- Q-1
-
How is the offset for the internal ISA bridge (IBU unit) set?
- A-1
-
This offset is automatically set internally, so there is no need for user settings.
Clock
FAQ-ID : VR4181-0006Last Updated : 2006/03
- Q-1
-
Can the system clock or subsystem clock be input without connecting a crystal resonator?
- A-1
-
Such clock input is possible if the system clock is input to the CLKX1 pin or the subsystem clock is input to the RTCX1 pin.
This is not recommended for ordinary use, however, since the PLL cannot be locked unless the system clock's frequency is 18.432 MHz.
Power modes
FAQ-ID : VR4181-0007Last Updated : 2006/03
- Q-1
-
In cases where power mode control does not have to be considered, is it OK to turn on the power supply to a peripheral device at the same time even though the SPOWER/MPOWER signal is not being used to control the power supply to SDRAM or external devices?
- A-1
-
Turning on the power supply to both at the same time causes the external device to be started during a reset period, but this is OK as long as there are no problems caused by this timing.
The MPOWER signal is used to turn off the 1.5-V power supply for the CPU in Hibernate mode.
Any device (such as ROM) that does not require input of a power supply during Hibernate mode can be controlled by the MPOWER signal.
Hazards
FAQ-ID : VR4181-0008Last Updated : 2006/03
- Q-1
-
Do any hazards occur when accessing general-purpose registers other than the CP0 register?
- A-1
-
No, no hazards occur when accessing any general-purpose registers.
Clock oscillator
FAQ-ID : VR4181-0009Last Updated : 2006/03
- Q-1
-
Are there any recommended oscillators or constants?
- A-1
-
Generally, the oscillator manufacturers have provided their evaluations of oscillation conditions.
However, such recommended conditions have not been requested or provided for evaluating this product.
As a reference example, see the following diagram that shows logic implemented in the VR4181A evaluation board.
This board uses the following crystal resonators.
X1: SX-6A (HokurikuElectric)
X2: MC-206 (SeikoEpson)
PC card controller
FAQ-ID : VR4181-0011Last Updated : 2006/03
- Q-1
-
In the VR4181 User's Manual, there is not anything about hot plug (hot swap) functionality. Is that supported?
- A-1
-
Like the VR4181A, the VR4181's PC card controller (ECU) can support hot plugging by using an isolation buffer that is used to isolate the buses for CompactFlash or PC Card from those for other devices.
The control signals for these products are described below.
VR4181A
- CF0_EN#/CF1_EN# signals and CF0_DIR/CF1_DIR signals
Used to control the isolation buffer.
- CF0_VCCEN# and CF1_VCCEN# signals
Used to control the card slot's power supply.
VR4181
- CF_DEN#, CF_AEN#, and CF_DIR signals
Used to control the isolation buffer.
- CF_VCCEN# signal
Used to control the card slot's power supply.
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