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Japan
VR4121..(uPD30121)
Contents
FAQ-ID : VR4121-nnnn
| 0001 | Memory burst mode settings |
|---|---|
| 0002 | RTS control |
| 0003 | Settings for using HSPM clock output |
| 0004 | DMA transfer mode |
| 0006 | Clock |
| 0007 | Reset |
| 0008 | Power modes |
| 0009 | Hazards |
Memory burst mode settings
FAQ-ID : VR4121-0001
- Q-1
-
I have created a breadboard combining the VR4121 and the Samsung 64 Mb SDRAM (K4S641632C-TC80) and performed evaluation, but burst write of SDRAM does not seem possible.
I use Pclock at 76.8 MHz, and VTClock at 26.2 MHz.
The burst mode settings for the VR4121 are described as interleave/burst length fixed to 2: does this have an effect?
- A-1
-
With a burst length of 2, the specification allows all types of accesses.
RTS control
FAQ-ID : VR4121-0002
- Q-1
-
I want to perform communication, but RTS control is not performed automatically, should I control it myself?
- A-1
-
Yes, this is necessary.
Settings for using HSPM clock output
FAQ-ID : VR4121-0003
- Q-1
-
What are the required register settings when using the HSPM clock output?
- A-1
-
As written in the VR4121 User's Manual 3rd Edition, the HSP function of the VR4121 involves a PCTEL patent, and use of this interface with other than PCTEL's software modem requires PCTEL's authorization.
Moreover, for the same reason, NEC Electronics cannot provide detailed information regarding this function.
Please generate the clock by some other means than HSP.
DMA transfer mode
FAQ-ID : VR4121-0004
- Q-1
-
Regarding performing DMA transfer with the AIU, it seems that there are no registers to perform transfer mode related settings such as burst/non-burst selection and burst length selection.
Is it correct to assume that the transfer mode is fixed?
- A-1
-
DMA transfer of the VR4121's AIU (audio interface unit) is 16-bit single transfer.
Moreover, the AIU-DMA transfer mode is fixed internally and cannot be changed.
Clock
FAQ-ID : VR4121-0006Last Updated : 2006/03
- Q-1
-
Can the system clock or subsystem clock be input without connecting a crystal resonator?
- A-1
-
Such clock input is possible if the system clock is input to the CLKX1 pin or the subsystem clock is input to the RTCX1 pin.
This is not recommended for ordinary use, however, since the PLL cannot be locked unless the system clock's frequency is 18.432 MHz.
Reset
FAQ-ID : VR4121-0007Last Updated : 2006/03
- Q-1
-
Can the POWER signal be set as active at the same time as the RTCRST# signal is being released?
- A-1
-
No, this is not possible.
As is shown in the RTC reset diagram in the User's Manual (Hardware), a period of at least 3RTC (= 92 us) is required between the rising edge of the RTCRST# signal and that of the POWER signal.
Power modes
FAQ-ID : VR4121-0008Last Updated : 2006/03
- Q-1
-
In cases where power mode control does not have to be considered, is it OK to turn on the power supply to a peripheral device at the same time even though the SPOWER/MPOWER signal is not being used to control the power supply to SDRAM or external devices?
- A-1
-
Turning on the power supply to both at the same time causes the external device to be started during a reset period, but this is OK as long as there are no problems caused by this timing.
The MPOWER signal is used to turn off the 1.5-V power supply for the CPU in Hibernate mode.
Any device (such as ROM) that does not require input of a power supply during Hibernate mode can be controlled by the MPOWER signal.
The SPOWER pin is used to turn off the SDRAM's power supply when supplying the power to the device for the first time.
When the power is supplied to the device, Hibernate mode is in effect until the POWERON signal becomes active after an RTC reset.
At this time, output to the data bus is at low level during this period.
This is because a pull-up resistor is required and the current consumption increases if the bus is in a high-impedance state.
However, since the status of the bus for SDRAM is undefined during the period from when the power is supplied to the SDRAM until the mode register is set, a conflict with the CPU's bus may occur during output.
The SPOWER signal is used to turn off the SDRAM power supply in order to avoid such conflicts.
However, most SDRAMs include a power-on reset function, which sets the device to high impedance immediately after the power supply.
In such cases, there is no need to use the SPOWER signal to control the power supply.
Hazards
FAQ-ID : VR4121-0009Last Updated : 2006/03
- Q-1
-
Do any hazards occur when accessing general-purpose registers other than the CP0 register?
- A-1
-
No, no hazards occur when accessing any general-purpose registers.
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