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CAN
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FAQ-ID : v85can-nnnn
CAN ; Message transmit/receive completion confirmation [V850/SF1]
FAQ-ID : v85can-0002
- Q-1
-
I would like to ask a question about how to confirm the completion of a message transmit/receive operation by the FCAN controller of the V850/SF1.
To make an interrupt to INTCTn or INTCRn occur upon completion, is an interrupt-enabled setting required for all of E_INT0 and E_INT1 of CnIE and IE of M_CTRLn ?
- A-1
-
An interrupt-enabled setting must be specified for all of the above when generating an interrupt (INTCTn, INTCRn) from the FCAN block.
However, to actually generate an interrupt in the CPU, you also have to clear the masks (such as CANMK3, CANMK2) in the interrupt control registers + (such as CANIC3, CANIC2).
When the CPU enters the interrupt-enabled state, an INTCTn or INTCRn interrupt is generated upon FCAN transmit/receive completion and the CPU transfers control to the interrupt handler.
CAN ; Transmit/receive completion confirmation [V850/SF1]
FAQ-ID : v85can-0003
- Q-1
-
How can I confirm the completion of a transmit/receive operation, without using an interrupt?
- A-1
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If IE of M_CTRLn is cleared or a mask is set for CANIC, no interrupt occurs in the CPU.
At this point, check the pending interrupts using the CnINT1/0 bit of CnINTP.
If the bit is set, clear it. In this case, E_INT0 and E_INT1 of CnIE must be enabled.
CAN ; Multiple internal register addresses [V850/SF1]
FAQ-ID : v85can-0004
- Q-1
-
In the V850/SF1 Hardware User's Manual, the address representation for internal registers is described as xxnFF804H n = 3, 7, B.
What does the value of n represent?
- A-1
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This only indicates that FCAN registers seem to be the addresses of n = 3, 7, and B.
In usual use, you can assume n = 3.
Because the I/F of FCAN is connected via an external bus and not all addresses are prepared as external addresses, you see an image.
CAN ; Settings in the various registers [V850/SF1]
FAQ-ID : v85can-0005Last Updated : 2006/04
- Q-1
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What are the settings in the various registers (CGCS, CnBRP, and CnSYNC)?
[Conditions] (1) Clock: 16 MHz (2) Baud rate: 500 kbps (3) Sampling point: approximately 75%
- A-1
-
Clock (fMEM) for CAN memory access controller is set by the MCPn flag in the CGCS register.
When MCPn is set to 0, for example, fMEM is fxx, which is the clock supplied to the microcontroller.
If a 16-MHz clock signal is connected, then fMEM = 16 MHz.
As shown in Figure 18-2 in the User's Manual, fMEM is connected to the baud rate generator and the global timer system clock generator.
This baud rate generator provides the basic baud rate setting for CAN.
The global timer system clock generator provides a time stamp function, which is an optional function that uses the CAN protocol.
- Q-2
-
What is the "CAN protocol layer main clock" in "18.4.25 CnBRP" in the User's Manual?
- A-2
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The CAN bit rate prescaler (fBTL) is set using the CnBRP register.
Using this register, set the bus type (high speed or low speed: 125kbps or lower) and time quanta, known as TQ in the protocol.
Example) When 500 kbps is used ...
In this example, assume the data bit width is 8TQ.
Therefore, 1TQ = 500k*8 = 4MHz = fBTL.
In the setting in the previous section, when 16MHz is supplied as the base clock, if BRPn = 1 (fMEM/4) is set, 4MHz is set.
By setting BTYPE = 1 at the same time, you can enter the high-speed mode.
- Q-3
-
What is the CAN bus baud rate in Section 18.12 in the User's Manual?
- A-3
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The CAN synchronization control register sets the bit time, SP (Sampling Point) and SJW.
Example) When 599kbps, SP = 75%
Because data bit width = 8TQ is set in the previous section, DBTn = 7 (fBTL*8) is set. If SP is 75%, 6TQ is set.
So set SPTn = 5 (fBTL*6).
For the SJW setting, up to 4TQ is allowed by the protocol.
However, in this example, because (DBT-SPT) = 2, the upper setting limit is 1.
CAN ; Bus-off occurrence and detection [V850/SF1]
FAQ-ID : v85can-0006
- Q-1
-
I want to detect a bus-off state in CAN communication by using the bus-off flag of the CANn control register.
How can I generate a bus-off state and detect it?
- A-1
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To generate a bus-off state, cut the connection with the transceiver, etc. and transmit with the CANRX pin of the microcontroller pulled up to high level.
In order to detect a bus-off state, we advise you to check the BOFF flag in the interrupt handler (INTCE1 or INTCE2) processing routine.
CAN ; Receive message is missing. [V850/SF1]
FAQ-ID : v85can-0007
- Q-1
-
Transmit/receive is executed asynchronously at a regular interval.
When the other party transmits messages in succession before receiving, the sequence of received messages gets out of order (a message is missing or overlooked).
- A-1
-
Judging from the occurring phenomenon (a receive message is missing), an overwrite to the receive message buffer may have occurred.
When a message is received after the DN bit is cleared in receive processing, the DN bit of the M_STATn register is set and an overwrite occurs.
This is indicated by the MOVR bit of the M_CTRLn register.
Check the DN bit of the M_STATn register at the end of the receive processing.
If the DN bit is not 0, try to get receive data again.
Also set the OVM bit of the CnCTRL register so as to enable new message overwrite (0).
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