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Japan
Other Peripheral Func
Contents
FAQ-ID : 78peri-nnnn
Control of real-time output ports
FAQ-ID : 78peri-0001
- Q-1
-
In the real-time output port block diagram for the uPD780054, a control signal is applied to the P12 output latch via RTBH, RTBL, and the internal bus. What are the contents controlled by the RTPM value?
- A-1
-
The block diagram does not show which data is written at what timing to the output latch; it only shows the data flow control.
In simple terms, the following operations occur depending on the RTPM value:
(1) In the case of bits for which RTPM is 0, the data on the internal bus is written to the output latch by writing to P12.
(2) In the case of bits for which RTPM is 1, the contents of RTBH and RTBL are written to the output latch at the timing indicated by the RTPC setting.
(The trigger source at this time is described in Table 20-3.)
Thus the change of RTPM triggers the data transfer.
Buzzer output procedure
FAQ-ID : 78peri-0002
- Q-1
-
Section 13.1 of the uPD780308 User's Manual (U11377) describes the buzzer output procedure.
Must I set P36 and PM36 each time?
- A-1
-
No.
If you want to make the buzzer output ON/OFF with the same buzzer output frequency, please manipulate bit 7 (TCL27) of the TCL2 register only.
What are the differences between INT0 to INT3 in the uPD780021A ?
FAQ-ID : 78peri-0003Last Updated : 2001/08
- Q-1
-
I am using the external interrupt function in the uPD780021A.
Do INTP0 to INTP3 have any different characteristics?
- A-1
-
INTP0 to INTP3 only differ in their default interrupt priority levels.
When the same priority level is set by the priority level specification flag register, and interrupts occur simultaneously, the INTP0 priority level is the highest and that interrupt will be acknowledged.
The INTP3 has the lowest priority level and that interrupt will be held.
Thus, use these interrupts according to the required interrupt level.
If timer/counter 1 output is prohibited, can P31 be used as a port? [78K/4]
FAQ-ID : 78peri-0004
- Q-1
-
In the uPD784216, if TOE1 of the TMC1 register is set to output disable, is it possible to use P31 as a port?
- A-1
-
If timer/counter 1 output is disabled, P31 can be used as a port.
There is no problem with such usage.
Setting of TOE1 of TMC1 register [78K/4]
FAQ-ID : 78peri-0005
- Q-1
-
I want to use the serial interface in the uPD784216 in asynchronous mode.
Referring to the block diagram (Figure 17-2), I see that TO1 must be input to the selector.
Is it necessary to set the TOE1 bit of the TMC1 register to 1 ?
- A-1
-
Regrettably, the description in the manual is insufficient.
In this case, setting the TOE1 bit of the TMC1 register is not necessary.
Simply select TO1 as the 5-bit counter input using the BRGCn register.
Which SFR specifies external wait for the wait function? [uPD78P4038]
FAQ-ID : 78peri-0006
- Q-1
-
There is a caution regarding the programmable wait control register (PWC1, PWC2) settings in section 23.2 Wait Function in the User's Manual to the effect that"Do not set external wait to the internal ROM area.With what register (SFR) are external waits specified?
Otherwise, the CPU may be in the deadlock status which can be cleared only by reset input".
- A-1
-
The MM register and PWC1 and PWC2 registers specify the wait function.
This caution means that the combination of the using an external wait set by PWC and fetching at the same speed as the external memory by setting IFCH of the MM register to 0 is prohibited.
Can both external wait and internal wait be enabled?
FAQ-ID : 78peri-0007
- Q-1
-
In the uPD784216A, I enable the WAIT pin (external wait) while accessing the external memory.
Can the internal wait signal also be enabled in addition to external wait?
- A-1
-
No it can't.
The external wait and internal wait must be used exclusively.
Effective timing of external input wait signal
FAQ-ID : 78peri-0008
- Q-1
-
Please describe the CPU's WAIT operation through the external input WAIT signal.
There are three types of times that are related to the fall of the external input WAIT pin for the CPU.
If any one of these three times exceeds the time range, does this prevent WAIT from being applied?
Input time from Address to /WAIT(tdwat) : (2+a)T-40 (MAX) Input time from ASTB to /WAIT(tdstwt) : 1.5T-40 (MAX) Input time from /RD to /WAIT(tdrwtl) : T-40 (MAX)
- A-1
-
No, if any one of these three times meets the specification, WAIT is applied.
The reason why three specifications are described is in order to facilitate judgment, regardless of which signal WAIT is generated from.
Please use the specification that is the easiest to understand for your particular system.
Can I/O ports and external interrupts be mixed in the same port?
FAQ-ID : 78peri-0009
- Q-1
-
P00 to P06 of the uPD784218 have an external interrupt request function in addition to an I/O port function.
Is it possible to use a mixture of the port mode and external interrupt request mode for separate bits?
- A-1
-
Yes, this can be done.
However, even during use as a port, interrupts occur as the result of port data changes.
So you must set the interrupt mask bit of the pins that are assigned as port pins to prevent the acknowledgment of unnecessary interrupts.
Port mode and port data settings when using alternate functions of port
FAQ-ID : 78peri-0010
- Q-1
-
In the uPD78421x, the port I/O status can be set using the port mode register.
Is it necessary to set the port mode register even when using port alternate functions?
(Address bus, data bus, UART, BUZ, etc.)
- A-1
-
Yes, this is basically correct.
However, regarding the external bus, the function is switched to address bus or data bus by setting the MM register.
So the port mode settings are not required.
When using UART, the mode of the ports corresponding to TxD must be set to output and 0 must be written to the output latch.
The mode of the ports corresponding to RxD must be set to input. Regarding BUZ, PM24 must be set to output and the P24 output latch must be set to 0.
Does a Schmitt trigger input pin work as a Schmitt trigger input in the case of normal ports as well as in the case of alternate functions?
FAQ-ID : 78peri-0011
- Q-1
-
In the uPD78F4225, when using the pins of the I/O circuit types 8-K and 10-I as input pins, does a Schmitt trigger input pin work as a Schmitt trigger input when the pin is specified as a regular port as well as when the pin is specified as an alternate function (timer, serial I/F)?
- A-1
-
Yes, this is correct.
The input buffer is the same in both cases.
For the input specifications of each port, refer to the DC characteristics in the data sheet.
uPD78932x ports [78K0/S]
FAQ-ID : 78peri-0012
- Q-1
-
In the uPD78932x, a 40-key key matrix is configured.
In a configuration of five input ports (KR00 to 03, INT) x 8 output ports (P80 to 85, P10, P11) = 40 keys, can standby be released at the falling edge of the INT/P61 port?
- A-1
-
Yes, this is possible.
An SFR illegal break occurs when standby is released.
FAQ-ID : 78peri-0013
- Q-1
-
An SFR illegal break occurs after the STOP mode is entered by execution of the 78K4 standby command (STBC) upon recovery from the standby status.
- A-1
-
There seems to be a problem with the STOP release method.
STOP mode can be released either by generating a vectored interrupt (the CPU is in the interrupt-enabled status) or without generating a vectored interrupt (the CPU is in the interrupt-disabled status).
Judging from the contents of your inquiry, you are employing the vectored interrupt generation release method.
Since the vector in this case has an area of only a 16-bit address, if 3 bytes are required for the interrupt jump destination, direct branching from the vector is not possible (a program loop occurs and the subsequent operation is unpredictable).
When the interrupt servicing routine is in an area indexed within 2 bytes, the interrupt servicing routine can be correctly branched to, so processing is possible as long as the interrupt servicing routine is correct.
Does the uPD789166 have a comparator? [78K/0S]
FAQ-ID : 78peri-0014
- Q-1
-
The uPD789166 Data Sheet has a description of the pin I/O circuits, and describes an N-ch open-drain output, and a 5V tolerant input buffer and comparator in type 13-X; but there is no description about the comparator.
- A-1
-
This comparator is used only for the SMB interface of the uPD789166Y, to check whether the SMB input signal is over the threshold or not.
The uPD789166 does not have an SMB interface.
Since no comparator is provided in the uPD789166, please ignore this.
Incidentally, this information is described in Figure 5-10 in the data sheet.
The input port cannot be normally read immediately after setting internal pull-up.
FAQ-ID : 78peri-0015Last Updated : 2001/11
- Q-1
-
To lower the power consumption of the uPD78P018FY, the port mode is set to the input mode and the internal pull-up resistor is enabled only when data needs to be read.
In this case, however, it is difficult to read the correct value.MOV PM1, #** MOV PM2, #** MOV PUO, #** MOV A, P1
- A-1
-
Even if the internal pull-up resistor is enabled, the resistance value is 40kΩ (90kΩ MAX), so because the charge-up of the capacitor of the pin includes the external wiring capacitance, it takes longer to charge up to high level than the instruction execution time.
As a result, correct values cannot be obtained even when the pull-up resistor is enabled and the port is immediately read.
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