NEC Succeeds in the World-Leading Development of a 4 Gbit DRAM

4-Gigabit DRAM

NEC is pleased to announce the world-first successful development of the world-first 4 Gbit DRAM. Its ultra-high capacity facilitates high-speed data transmission and makes it the optimum memory device for handling the animation image and voice data associated with multi-media applications.

The 4 Gbit DRAM integrates approximately 4.4 billion elements on a single chip to achieve a memory capacity sufficient to store the equivalent of about a year and a half's worth of newspaper information (16,000 pages) and equivalent to a CD-ROM providing 47 minutes of full-motion images or 6 hours of audio.

The newly developed 4 Gbit DRAM is the result of leading-edge technology such as

the use of the 0.15 micron CMOS process;
"multi-value technology" capable of memorizing 2 bits of data in a single memory cell;
the development of a novel circuit technology, including a capacity-linking sensing amplifier allowing chip surface reduction as well as the development of a self-generating write-in power supply and a time-sharing multi-value sensing system;
the development of a high-dielectric constant BST capacitor capable of improving the data storage capacity available per memory cell.

Based on these technologies, it has been possible to achieve a major reduction in chip surface area to a 985.6 sq.mm, only 49% of the surface required with conventional technology. At the same time, chip cost has been reduced to a tenth compared with the prior state of the art. It has also been possible to achieve the high data transfer speed of 1 Gbits per second that is essential for file memory.

NEC believes that the newly developed 4 Gbit DRAM will be a key device in meeting the current need for high capacity, and high-speed operation. In readiness for the shipment of samples targeted for the year 2,000, commercial product development is rapidly taking shape.

The memory capacity required for computers is constantly being expanded as greater MPU speed and further OS development are realized. With the advent of the multimedia age in its fullest sense it can be anticipated that memory capacity will continue to expand in order to meet the memory needs for home servers as well as moving image and audio (voice) processing systems.

Much of the progress made in upgrading DRAM capacity is due to the advances made in ultra-fine machining technology. With each generation, progress has been marked by a 70% reduction in the minimum machining dimensions. Already, micro-machining has advanced to precision levels below the wavelength of light. This has brought the technology close to its theoretical limits. To achieve further progress in upgrading memory capacity, it will therefore be necessary to establish a high-density technology that does not depend on micro-machining technology. The multi-value technology developed by NEC on this occasion has doubled the effective memory size by storing 4 Gbits of data in 2 Giga memory cells. Through the development of its original high-density technology, NEC has been able to achieve two essential benefits at the same time: a large-capacity memory and the low cost that is critical for widespread market penetration.

The most salient technical features of the newly developed 4 Gbit DRAM can be summed up as follows:

(1) Multi-Value Technology

A DRAM memory cell stores data in the form of electrical charges. In the conventional systems, a single memory cell would store only 1 bit/binary data. In other words, the conventional memory had only two states, one in which the memory was completely full and one in which it was totally empty of electrical charge. The full/empty states corresponded to the 1 and 0 values of the binary data codes to record 1 bit of data.

The multi-value technology adds to these two full-empty states an intermediate state to enable the storage of multiple values. In the case of the newly developed 4 Gbit DRAM, a total of four levels of electrical charge storage have been provided. This has made it possible to store 2 bits of data in a single memory cell. In practice, this means that the number of memory cells to store the same data has been halved from the 4 Giga to 2 Giga cells. This can be paraphrased by saying that the effective memory size has been doubled.

(2) Capacity-Linking Sensing Amplifier

Each memory cell has four levels of electrical charge that can be stored as data. For data readout, it is thus necessary that a decision is made to determine which of these charge levels has been stored. The amount of charge is proportional to the voltage of the memory cell. If the maximum voltage that can be stored is taken as Vcc, then the four charge storage stages correspond to Vcc, 2/3 Vcc, 1/3 Vcc and 0, respectively.

A suitable reference voltage is provided for accessing these voltages during data readout to compare the stored charge quantity with this reference voltage. To differentiate between the charge levels Vcc and 2/3 Vcc, for example, the intermediate stage 5/6 Vcc is used as the reference voltage. In order to differentiate the four values above (that is, Vcc, 2/3 Vcc, 1/3 Vcc, and 0) it will be necessary to have the three reference voltages: 5/6, 3/6, and 1/6 Vcc.

The newly developed capacity-linking sensing amplifier performs the readout operation in two stages. First, it compares the stored charge with the 1/2 Vcc voltage, the value mid-way between the maximum and minimum values. If it is found that the stored data is greater than 1/2 Vcc, the next comparison stage is against the 5/6 Vcc reference value. If, on the other hand, the first comparison shows that the stored data is smaller than 1/2 Vcc, the second stage comparison is against the 1/6 Vcc reference voltage.

This sensing amplifier is unique in that it uses capacity linking to generate automatically the required reference voltage - whether 5/6 or 1/6 Vcc - required for the second-stage readout operation in accordance with the outcome of the first stage readout. With this approach, it is possible to simplify the sensing amplifier circuit giving a reduction to a third of its conventional size. This has helped to achieve a greater compactness in implementing the circuit in a very small area.

(3) Self-Generating Write-in Power Source

A direct random access memory or DRAM has the characteristic that once data has been accessed or read-out from the memory it is destroyed and therefore rewriting is required. As the write-in level uses a multi-value system it is necessary to have four levels, namely, Vcc, 2/3 Vcc, 1/3 Vcc, and 0. The newly developed re-writable DRAM memory is capable of generating these four levels by using the bit line capacity ratio. Re-writing the data into the memory takes place through the bit line. For this re-writing process, the bit line is divided so that its capacity ratio is 2 : 1. The high-order bit data is entered on to the bit line with the larger capacity and the low-order bit data onto the other bit line. After this, the switch used for dividing the bit line is closed and the electrical charge stored on the two bit lines are added. Since the bit line capacity ratio is 2 : 1 the high-order and low-order bit data are weighted 2 : 1 for totaling and the re-writing levels corresponding to the data are generated on the bit line.

Thanks to the use of this system it has been possible to dispense with a dedicated power source for generating the write-in levels and thereby reduce the circuit area to give improved compactness.

(4) Time-Sharing Multi-Value Sensing System

The DRAM memory cell is connected to the bit line and to access the signals in it an amplification device known as a sensing amplifier is provided on each bit line. Since the number of memory cells that can be connected to a single bit line is limited, a 4 Gbit DRAM requires several million sensing amplifiers. Since the newly developed 4 Gbit DRAM, however, stores multi-value data into the memory cell so that an even greater number of sensing amplifiers would be required. To reduce the number of sensing amplifiers in the new4 Gbit DRAM they are operated on a time-sharing basis so that one sensing amplifier is capable of accessing the signals of four bit lines. In this manner, a single sensing amplifier performs the duty of four amplifiers. The result is that in combination with the technology described in (2), it has been possible to reduce the number of sensing amplifiers to a twelfth as compared with conventional technology.

(5) High-Dielectric Capacity Film

To permit the input of multi-value data into the memory cells it is essential that the storage capacity of the memory cells should be increased. This requirement has been met by the development of a 60fF (femto-Farad) memory capacity. Its memory cell uses a storage capacity film consisting barium-strontium titanate (Ba,St)TiO3, a material with a high dielectric constant to permit the creation of a larger storage capacity, given the same surface area.

After the successive advances marked by the development of the 256 Mbit and 1 Gbit memory, NEC has made a new breakthrough with its world-first 4 Gbit memory. With an ongoing commitment to develop and create ever more advanced state-of-the-art devices, NEC is engaged in active research and development as part of its corporate mission to serve society and its further development.

NEC intends to make public its latest success on February 6 at the 1997 International Solid-State Circuit Conference (ISSCC 97) due to be held in the United States from this date.

The attached document gives the main technical specifications of the newly developed product.