Release of 4M-Bit Bi CMOS Synchronous SRAM for Cash-Memory Use

µPD464318L/36L and µPD464518L/36L

NEC has commercialized and will commence sample shipment of 4 types of 4M-bit Bi CMOS synchronous high-speed SRAM, ideal for cash-memory use in RISC processors for high-end work stations from January next year. They are the "µPD464318L/36L" and "µPD464518L/36L".

The new products can be divided into two types, 256K word x 18 bit configuration, and 128K word x 36 bit configuration, but all come loaded in a 119 (7 x 17) pin plastic BGA package. Their main distinctive features are,

since they employ 0.35 µm Bi CMOS miniature processing technology. they combine a large volume of 4M bits with a high-speed movement of 200MHz.,
as they use HSTL(*1) and LVTTL (*2) as interfaces with microprocessors, they are compatible with a wide range of RISC processors.

The price of the new products is 20,000 yen to 25,000 yen per unit, depending on bit configuration and clock access time. Mass-production and shipments are planned to start from April 1997.

In recent years the field of adaptation of high-speed SRAM as cash-memory for super computers, general-use computers, work stations as well as personal computers, and also as buffer memory for measuring instruments and telecommunications equipment, has greatly enlarged. The introduction of optimum cash-memory-use high-speed SRAM for the purpose of demonstrating to maximum advantage the performance of each processor was particularly desired to accompany the recent diversification in microprocessors.

The new products have been devised to meet this kind of need.

Main features of the new products are as follows:

(1) The utilization of 0.35 µm Bi CMOS fine processing technology.: Utilizing 0.35 µm Bi CMOS fine processing technology, the new products, by virtue of 3-layer polysilicon/2-layer aluminum wiring structure, as well as optimization of layout and high-speed technology, realize a large volume of 4M bits and a maximum high-speed movement of 200 MHz.
(2) Providing the product compatibility with both HSTL and LVTTL interfaces.: As the products are compatible with HSTL and LVTTL interfaces, they are compatible with a broad range of microprocessors.
(3) 18-bit/36-bit configuration.: The products feature both the 18-and 36-bit parity-bit configurations generally used in work stations .
(4) Support of two types of synchronous mode (µPD464318L/36L): Two types of synchronous mode can be selected by the external terminal: (1) dual-clock input register/ dual-clock output latch mode and controlled by two clocks, main clock and exclusive output clock, and (2) single-clock input register/ single-clock output register controlled by main clock only.
(5) High-speed access time.: Clock access time with the input register/output latch type is 7.0, 8.0. 9.0 nanoseconds (operation frequency : 200, 167, 143 MHz), and with the input register/output register type 2.5, 3.0, 3.5 nanoseconds (operation frequency : 200, 167, 143MHz).
(6) Utilization of late write method.: The new products utilize a late write method where the write-read interval dummy-cycle can move at 1 cycle, and which is compatible with high-speed operation.

See the attachment for the main specifications of the new products.

(*1) : HSTL(High Speed Transistor Logicxi)
(*2) : LVTTL(Low Voltage TTL)