Release of High-complexity, High-speed, Low-power-consumption CMOS Cell-base IC Realized by Vanguard Process

The new device has the following features:

(1) at most 1.6 million gates at the maximum on-chip usable gates which is 1.6 times larger than our existing device,

(2) low power consumption of 0.7µW/gate at 1MHz which is about 45% smaller than our existing devices,

(3) new cores such as DSP and high speed multiplier in addition to a RISC-type MPU for expanding the library for widening the range of applications.

Since the cell-base IC which is in between the gate array and the full custom LSI is less expensive in development fee and takes a shorter period for development meeting with customers' needs than the full custom LSI and advantageous over the gate array in integrating more functions, it is gaining popularity in the ASIC market.

We introduced to the market the genuine cell-base IC "CB-C7 Family" in March, 1991 and "CB-C8 Family" for which 0.5µm process was adopted in September, 1993 to satisfy users' needs.

In recent years, as portable equipments such as high performance notebook personal computers and portable telephone sets are rapidly proliferating, the demand for smaller equipments and low power consumption is gaining momentum. The communications equipments and personal computers need an ASIC which will operate at 100MHz or more. Further, as the era of multimedia is heralded and evolving in a high pace, there are more needs for "system on silicon" by a large-scale core for modulation/demodulation for communication and image processing. The new product will be able to offer a solution for the needs by a variety of core line-up.

The major features of the new device are as follows.

1. High complexity and high speed

At most 1.6 million usable gates (2-input NAND) which is about 1.6 times greater than our existing devices.

The delay time of internal gate at 3.3V is 113ps (2 fan-outs, standard wiring length) which is faster than our existing products by about 35%.

2. Low power consumption

Thanks to 0.35µm process, power consumption is 0.7µW/gate (about 45% smaller than our existing products) at 3.3V, 1MHz. Further, a 2.5V device will be available in the fourth quarter of 1995 which will be able to contribute to further lower-power-consumption portable equipments.

3. Variety of cores and interfaces (including those under development)

     CPU                   : V30MX *1
                             RISC-type MPU *2
     Peripheral            : CPU-peripheral macros such as 
                             UART *3, timer
     Memory                : single port/dual port RAM, ROM
     Data path macro       : macros such arithmetic logic unit (ALU), 
                             high speed multiplier
     High-performance macro: DSP, MPEG2, AC3 *4 decoder
     Analog                : PLL, A/D converter, D/A converter
     High speed interface  : PCI *5, GTL *6, HSTL *7, PECL *8,
                             Rambus(TM) ASIC CELL *9

4. Multiple pin package

At most 304 pins for QFP and 528 pins for PGA. Tape BGA for at most 696 pins is under development (the shipment will be available at the end of 1995). Particularly, at most 1200 pad (including power supply and ground) can be arranged on the chip, therefore a package having more pins will be able to be supplied.

5. A design technology which enables a large-scale circuit is adopted

In addition to variety of functional blocks suitable to design by logical synthesis, a scan path which facilitates the check of internal circuit which becomes difficult as its scale is enlarged is supported.

Further, the following environments can be offered by our ASIC CAD system "Ope nCAD V4.3":

(1) A data path having arithmetic circuits such as multiplier and adder can be integrated automatically.

(2) High accuracy clock tree synthesis (CTS) which can keep the siganl skew inside LSI at 100ps or less is supported.

(3) Since high-accuracy predicted wiring length information is given to the logical synthesis tool by a floor plan, circuit design can be done without looking back the fin ished portions.

(4) Simulation considering postwiring adjacent intersecting capacitance which arises by the process as fine as 0.35µm can be done.

(*1)V30MX:

V30MX is a cell-base IC-dedicated CPU core, software-compatible with V20HL/ V30HL.

(*2)RISC-type MPU:

Our 32-bit RISC-type MPU "V8XX series"
Our 64-bit RISC-type MPU "VR4XXX series"

(*3)UART:

Universal Asynchronous Receiver Transmitter

(*4)AC3:

Voice compression/expansion standards proposed by Dolby Laboratories

(*5)PCI:

Peripheral Component Interconnect (interface standards proposed by Intel)

(*6)GTL:

Gunning Transceiver Logic

(*7)HSTL:

High Speed Transceiver Logic

(*8)PECL:

Pseudo Emitter Coupled Logic

(*9)Rambus(TM) ASIC CELL:

Trademark of Rambus, Inc., small amplitude interface standards for high speed data transfer