Release of High-speed, Low-power Consumption, High-complexity BiCMOS Gate Array

Thanks to the newly developed 0.44µm low-cost BiCMOS process technology and new BiCMOS circuit technology, the new family has the following features:

(1) ultra-high-speed operation tantamount to 0.35µm CMOS,

(2) 0.33µW(@frequency 1MHz, when operation rate 30%) power consumption per gate which is comparable to 0.35µm CMOS,

(3) high complexity due to new BiCMOS circuit technology, and

(4) high-speed interface operating up to 250MHz.

Since the BiCMOS gate array is featured with high-speed operation and high driving capability, it has been used as a key device for the data processing equipments, communications equipments, and measuring instruments. However, it has not been meeting users satisfaction with respect to power consumption, complexity, and price. On the other hand, since much higher data processing speed and communications capacity are required as multimedia evolves, device performance equivalent to BiCMOS is demanded.

The new device is developed in response to the above stated needs. That is, high-speed BiCMOS sells for a price of CMOS. Therefore it is suitable to the multimedia equipments and ATM equipments for which high speed is essential.

The major features of the new device are as follows.

(1) High-speed operation and low power consumption

· High-speed operation equivalent to 0.35µm device

The delay times of internal gate are 117psec (one fan-out, standard wiring length) and 142psec (two fan-outs, 2mm wiring length) for 2-input NAND and 240psec (one fan-out, standard wiring length) for D flip-flop; and the toggle frequency of flip-flop is 670MHz. Thus, its operating speed is 1.4 times higher than that of conventional 0.5µm CMOS gate array and is comparable to that of 0.35µm CMOS.

· Low power consumption tantamount to 0.35µm device

Ordinary AC power consumption is 0.33µW per gate (operation rate 30%, 1MHz) which is lower than the conventional 0.5µm CMOS gate array by 30% and equivalent to the 0.35µm CMOS device.

(2) BiCMOS device having competitive price with CMOS device Since

· the size of the MOS transistors in the logic section is made small to the limit and the bipolar transistors drive a load and
· process time is shortened by 30% by high energy ion injection technology to lead to a low-cost process, the price of the BiCMOS gate array which has been a few times higher than that of the CMOS device can be reduced to an equal price for the latter.

(3) High complexity

By employing a new BiCMOS circuit technology which gives a high driving capability equivalent to the conventional driving block with a low-power-consumption circuit block, the percentage of chip surface occupied by the high-drive block, which has been using a great percentage of the chip, can be reduced. Therefore, complexity is improved at the time the circuits are fabricated on the gate array.

(4) Equiped with high-speed multi-level interface

High-speed interfaces such as GTL, PECL, HSTL, and PCI as well as LVTTL are provided. The bipolar transistors are placed at essential portions, which enables 200MHz operation for GTL and 250MHz operation for PECL and HSTL.

(5) Possible development in standard design environment of NEC's gate array

Since the functional blocks are common to NEC's CMOS gate array series and the standard design environment "Opencad V4.3" for NEC's gate array can be used, the circuits can be designed in an identical manner to CMOS gate array.

(6) Variety of package types

Variety of package types are available such as QFP (mainly 208 pins) up to 304 pins, PGA up to 528 pins, and BGA up to 480 pins.

Refer to the attachment for the major specifications of the new device.

(*1): QB:

Quadruple Advantageous BiCMOS; High Speed, Low Power, High density, Low Price