| Press Release *****For immediate use August 26th, 2002 NEC Introduces High-Performance, Low-Power Embedded DRAM for SoC Design-Standard CMOS-Compatible Embedded DRAM Process Enables Easy Integration of Hard Cores or Soft Macros-
TOKYO, SANTA CLARA, Calif. and DUESSELDORF, Germany, August 26, 2002 - NEC Corporation (NASDAQ: NIPNY) and its wholly owned subsidiaries in the United States and Europe, NEC Electronics Inc. and NEC Electronics (Europe) GmbH., today announced the availability of 0.13-micron (drawn) embedded DRAM technology based on NEC's high-performance embedded DRAM process. Operating at 1.2 volts (V), NEC's embedded DRAM has a typical random access speed of up to 314 megahertz (MHz) with one clock latency and a typical page-mode access speed of 595 MHz, making it ideal for complex system-on-chip (SoC) designs in communications, consumer and high-end computing applications that require high speed, low latency and low power consumption. NEC's embedded DRAM is available in 8- and 9-megabit (Mb) hard macro cores as well as routable configurable macro cores, giving designers the flexibility to use a variety of embedded DRAM within a single SoC. NEC's low-k dielectric embedded DRAM copper process is fully compatible with its standard CMOS process, which means that designers can easily integrate standard embedded DRAM with NEC's CMOS-based intellectual property. "NEC is committed to delivering key ASIC technologies such as embedded DRAM that ensure high performance and reliability for our customers," said Kyuichi Hareyama, general manager, Network Core LSI Development Division, NEC Electron Devices, NEC Corporation. "With our high-speed, low-power embedded DRAM and CMOS-compatible process technology, our customers now have the opportunity to create truly high-performance, differentiated products required by the next generation of systems." According to market research firm, In-Stat/MDR, worldwide merchant market dollar shipments of highly complex, cell-based designs containing at least one or more blocks of DRAM, in conjunction with other embedded functions, will grow from $95 million in 2001 to $250 million by 2006, a CAGR of 21 percent. Broad Range of Embedded DRAM Solutions Unlike its commodity DRAM process, NEC's embedded DRAM process uses the same structure as its standard CMOS process, and thus is fully compatible with that process. This compatibility dramatically reduces turnaround time by minimizing the number of process steps needed to add embedded DRAM. With today's announcement, NEC offers embedded DRAM solutions to support customers using the company's CB-12 and CB-130 ASIC libraries. The CB-12 embedded DRAM operates at 1.5 volts and up to 222 MHz (typical) in random access mode with the one clock latency typically featured in fast SRAM solutions. The CB-130 embedded DRAM operates at 1.2 volts and up to 314 MHz (typical) in random access mode with one clock latency. The NEC embedded DRAM process achieves these unprecedented speeds and power consumption levels by keeping parasitic resistance and capacitance low. NEC's embedded DRAM macro uniquely allows embedded DRAM blocks to be rotated to any orientation on a chip, simplifying integration with other on-chip components while preserving the performance and power consumption benefits afforded by NEC's process. Additionally, the upper metal layers of an ASIC can be routed over the top of embedded DRAM blocks, simplifying chip design, improving timing and conserving silicon. NEC's embedded DRAM is ideal for consumer products such as hand-held wireless devices and cell phones, high-end networking systems including ATM switches and routers, and business tools such as printers and PC graphics cards. Availability About NEC Electronics Inc. About NEC Corporation About NEC Electronics (Europe) GmbH ***
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