Main Specifications of the CB-130 Family
| Process |
Gate length: 0.095 um, silicon gate CMOS
All-layer Cu wiring: 5 layers/6 layers (CB-130L library)
5 layers/6 layers/7 layers (CB-130M library)
8 layers/9 layers*1 (CB-130H library) |
Max. number of
mountable gates |
62 million (when CB-130M library used) |
| Max. I/O number*2 |
2800*2 (when CB-130H
library used) |
| Power supply voltage |
Internal: 1.2 V
I/O block: 1.8/2.5/3.3 V |
| Power consumption |
About 5 nW/MHz/gate (when CB-130L library used) |
| Delay time |
Inverter |
9.5 picoseconds (fan-out: 2, standard block) (when
CB-130H library used) |
|
2NAND |
12.8 picoseconds (fan-out: 2, standard block) (when
CB-130H library used) |
| Output drive capability |
Up to 24 mA |
| RAM macro |
Single-/dual-port SRAM (compiled type)
Loadless 4T-SRAM, FIFO, CAM, ROM, DRAM, FLASH |
| Interface |
1.8/2.5/3.3 V interfaces
Low-noise buffer
High-speed interfaces (PCI, PCIX, HSTL, LVDS, GTL+, AGP, SSTL, SerDes,
etc.) |
Cores
Communications field
Graphics field
Mobile field
Home electronics field
Common to all fields |
Network controller
ATM*1, Ethernet, xDSL
DRAC, 2D/3D accelerator, NTSC/PAL encoder
DSP, speech codec
PCI controller, USB, IEEE1394, MPEG2
encoder/decoder, JPEG, modem codec
Digital PLL, analog PLL, UART, register file, scan, JTAG, FIFO,
CAM, ROM, A/D converter, D/A converter, V850E CPU, VRxxxx CPU |
| *1: |
The 9th layer of
9-layer products and the 8th layer
of 8-layer products are used as pads for the flip-chip mounting
package. |
| *2: |
The number of usable signals differs depending on
the package used. |
|
