Press Release
(STORY ORIGINATES IN San Francisco, CA)
*****For immediate use February 8th, 2000

NEC Develops Low-Cost, High-Speed 16Mbit Four-Transistor SRAM Macro For System-on-a-Chip Applications

NEC's load-less four-transistor was made possible by combining newly developed device and circuit technologies: an end-point dual-pulse driver (EDD) scheme for achieving stable data hold and minimum cycle time; a word-line-voltage-level compensation (WLC) circuit for stable static data hold; and an all-adjoining twist bit-line scheme to reduce bit-line (ATBL) coupling capacitance.

NEC's new technologies enable the development of low cost and high-performance system LSIs, which employ logic and memory components on a single chip. Using the four-transistor SRAM macro, the delivery time of system LSIs will be shortened, making it possible to bring the device to the market at the same time as standard logic components are released.

Demand for the development of advanced system LSIs is growing as the performance of components such as CPUs and graphics processors improves. However, the conventional six-transistor SRAM macro, which is used for a system-on-a-chip applications, cannot offer larger memory densities without significant increases in cell size despite its cheap production costs thanks to the use of standard logic process technology.

On the contrary, a DRAM macro, which can be offered at 1/8 of the cell size compared to a six-transistor SRAM macro, is costly and takes more time to manufacture since DRAM macros require a unique process technology, which is completely different from the logic process technology.

NEC has successfully developed the SRAM macro in response to the market demand for large-capacity, high-speed memory macros that reduce cost and improve delivery time, and which coincide with the release of standard logic.

Regarding the new SRAM macro as a core technology in the system-on-a chip era, NEC plans to accelerate the research and development of this new technology in order to bring it to the market as early as possible.

The results of this research will be presented at the International Solid State Circuit Conference 2000, being held in San Francisco on February 8.

Specifications of the load-less four-transistor SRAM macro
Organization:	512Kw x 32b
Access time:	2.5 ns
Power consumption:	1.1W @ 400 MHz, 1.8 V
Supply voltage:	1.8 V
Process technology:	5-Metal, 0.18m CMOS
Cell size:	1.04 x 1.86 m2
Chip size:	10.4 x 5.2 mm2

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About NEC Corporation
NEC Corporation (NASDAQ: NIPNY) (FTSE: 6701q.l) pioneered the concept of C&C, the integration of Computers and Communications, and is the only company in the world to be counted among top ranking corporations spanning the wide range of fields essential for this vision of multimedia: computers, communications and electron devices. Employing in excess of 150,000 people around the world, NEC saw net sales in fiscal year 1998-99 amount to 4,759 billion yen (approx. US$40 billion). For further information, visit the NEC home page at: http://www.nec-global.com

                        Media Contact:
                        Aston Bridgman
                        NEC Corporation
                        TEL   :81-3-3798-6511
                        FAX   :81-3-3457-7249
                        E-mail:Aston_Bridgman@HO-PRD.ccgw.nec.co.jp