Main features of the CB-12-series
1. Choice of Four Libraries To Meet Exacting Customer Requirements:
| Target: |
Library: |
Operating Frequency: |
| Low power consumption: |
L |
Up to 100MHz |
| Standard performance: |
M |
100-250MHz |
| High speed performance: |
HM |
250-450MHz |
| Ultra high speed performance: |
H |
450MHz + |
2. 4T SRAM:
4 transistor SRAM macro currently in development will enable reduced embedded
SRAM surface area by up to 30% compared to current 6T SRAM.
3. Optimized Line-up of IP Cores:
| Library: |
Core: |
| L library: |
V850E etc. |
| M library: |
DSP etc. |
| HM library: |
VR-series etc. |
Other cores and system IP in development for optimized solutions.
Please see <Attachment2>(IP
Core Lineup for the CB-12) for further details.
4. Deep integration, high operating frequencies, low power consumption:
- Integration of up to 32 million, 2-input NAND compatible gates.
- Power supply of just 1.5V, delay time is just 11.1 pico seconds (Fan
out 2) using HM library.
- Power consumption is a measly 7.3nW per 1MHz per gate when using
low power consumption L library, or approximately half that achieved
with NEC's previous products.
5. Leading-edge Packaging:
A full range of packaging for large pin counts, from flip-chip packaging
to chip size packaging (CSP) and standard packages including:
| Package: |
Pin count: |
| PBGA: |
max. 672 pins |
| TBGA: |
max. 1088 pins |
| QFP: |
max. 376 pins (0.4mm pitch) |
| Flip-chip: |
max. 3,000 pins |
| CSP: |
max. 600 pins |
|
