Register Setting Sequence

Are there any general cautions I should observe regarding the register setting sequence?

A certain sequence must be observed for the settings of the peripheral functions built into the microcontroller.
If this sequence cannot be observed, these functions may not work, illegal values may be output externally, and abnormal operation may result.
If no particular sequence is specified for a given peripheral function, basically set according to the signal transmission order.

Do you have any recommendations (or rules) regarding the setting sequence for the timer control register?

The target registers are the following:

First set the mode, and then set the compare registers.

I use the 3-wire serial interface of the uPD780034A switching between the slave reception mode and the master transmission mode, but the clock output immediately after switching to master transmission does not go well.
There is no problem for clock output when continuing to transmit.

The settings I use are as follows.

Since the P2n latch specification is 0 in the manual, when the port mode (PM2) and latch (P2n) settings are performed first, a low level is output to SCK30.

This is the expected operation.
When serial operation is not enabled with CSIM30, the pin operates as a port.
If the port is output and the output latch is 0, a low level is output to the pin.

In order to avoid this, set the port to output with the output latch set to 1, enable serial operation by setting CSIM30, and then set the output latch to 0.