VR4131..( uPD30131 )

Can SRAM be mapped to the SDRAM area (0 to 7FFFFFFH)?

The SDRAM area is for SDRAM only, and operation is not guaranteed if it is connected to any other type of device such as SRAM.

Is wait control possible for SDRAM?

There is no external wait control function for the SDRAM area.
However, in an external I/O area (selected by IOCS0# and IOCS1#), wait control can be implemented using the IORDY pin.
It is also possible to connect an SRAM to this area.
Note, however, that the following restrictions apply when SRAM is connected.

[Restrictions on SRAM connection]
Data errors can occur when a double-word write or cache write-back operation is performed in an external I/O area.

Error conditions:

1. When a double-word write or cache write-back occurs immediately after read or write access to an on-chip register (Note).
   
2. When a double-word write or cache write-back occurs while bus hold status is in effect.
   

[Avoidance methods]
Execute one of the following.

1. Execute a dummy non-cache read operation to the external I/O space at the start of the interrupt vector and immediately after read or write access to an on-chip register (Note).
   This avoidance method is effective when the bus hold function is not being used.
   
2. Execute a dummy non-cache read operation to the BCU register at the start of the interrupt vector and immediately after read or write access to an on-chip register (Note).
   This avoidance method is effective when the bus hold function is not being used.
   
3. Do not use the external I/O space as the data cache area and do not perform double-word write operations in this area.
   

Note  The following registers are excluded.

SCU register	0x0F001000 - 0x0F001009
SDRAMU register	0x0F000400 - 0x0F000409
PCIU register	0x0F000c00 - 0x0F000d43
BCU register	0x0F000000 - 0x0F000017

Is access enabled when the memory configuration includes both 16-bit and 32-bit memory?

The data bus width of ROM and SDRAM is determined by the status of the DBUS32 pin when a reset is canceled, and the same bus width must be set for both.
When a 32-bit data bus width is set via the DBUS32 pin, the width of the external I/O area (the area accessed via the IOCS0 and IOCS1 pins) can be selected as 16 bits or 32 bits.

However, when memory is connected to the IOCS0 and IOCS1 pins, the strobe signal used for control must be generated externally.
Also, some restrictions apply if memory is connected to the external I/O area and mapped to the cache area.
For details, see the use restrictions document distributed to NEC Electronics sales representatives.

Can the system clock or subsystem clock be input without connecting a crystal resonator?

Such clock input is possible if the system clock is input to the CLKX1 pin or the subsystem clock is input to the RTCX1 pin.
This is not recommended for ordinary use, however, since the PLL cannot be locked unless the system clock's frequency is 18.432 MHz.

Can the POWER signal be set as active at the same time as the RTCRST# signal is being released?

No, this is not possible.
As is shown in the RTC reset diagram in the User's Manual (Hardware), a period of at least 3RTC (= 92 us) is required between the rising edge of the RTCRST# signal and that of the POWER signal.

In cases where power mode control does not have to be considered, is it OK to turn on the power supply to a peripheral device at the same time even though the SPOWER/MPOWER signal is not being used to control the power supply to SDRAM or external devices?

Turning on the power supply to both at the same time causes the external device to be started during a reset period, but this is OK as long as there are no problems caused by this timing.

The MPOWER signal is used to turn off the 1.5-V power supply for the CPU in Hibernate mode.
Any device (such as ROM) that does not require input of a power supply during Hibernate mode can be controlled by the MPOWER signal.

The SPOWER pin is used to turn off the SDRAM's power supply when supplying the power to the device for the first time.
When the power is supplied to the device, Hibernate mode is in effect until the POWERON signal becomes active after an RTC reset.
At this time, output to the data bus is at low level during this period.
This is because a pull-up resistor is required and the current consumption increases if the bus is in a high-impedance state.
However, since the status of the bus for SDRAM is undefined during the period from when the power is supplied to the SDRAM until the mode register is set, a conflict with the CPU's bus may occur during output.

The SPOWER signal is used to turn off the SDRAM power supply in order to avoid such conflicts.
However, most SDRAMs include a power-on reset function, which sets the device to high impedance immediately after the power supply.
In such cases, there is no need to use the SPOWER signal to control the power supply.

Do any hazards occur when accessing general-purpose registers other than the CP0 register?

No, no hazards occur when accessing any general-purpose registers.

When CSI is operated in transmit and receive modes (TRMD = 1 in the CSI_MODEREG register), how can I start a DMA transfer for reception?

For either transmission or reception, transfers are not possible unless the transfer data is all there.
A DMA transfer for transmission and reception can be started automatically once T_FIFOE and T_DMAEN have been set.
Since transmission and reception occur at the same time, "the transmit data count = receive data count" and the receive data count can be controlled if a trigger is used with the transmit data.

Although DSIU is used for debugging, can it also be used as an ordinary SIU?

Yes, SIU and DSIU can be used as two serial ports.
This is also the case for the DSIU in other VR Series devices.

Is PCI access possible between SDRAM and a peripheral device?

No, PCI access to peripheral devices is not supported.