VR4122..( uPD30122 )

After the Hibernate mode is entered by executing the HIBERNATE instruction, does the system start up with some interrupt and recover from the Hibernate mode?

Once the system goes into the Hibernate mode, recovery to the Fullspeed mode is done through

After the Hibernate mode is entered by executing the HIBERNATE instruction and recovered from by an interrupt, can the program counter recover at the next step following the HIBERNATE instruction and the program be executed from where it left off?
(Using the RX4000.)

Since, when recovering from the Hibernate mode, a reset is input to the VR4122, execution occurs from the reset vector.
In order to resume execution from where it left off, save the current execution status in its entirety by software before Hibernate mode is entered, and then restore the saved items after recovery from the Hibernate mode.

In cases where power mode control does not have to be considered, is it OK to turn on the power supply to a peripheral device at the same time even though the SPOWER/MPOWER signal is not being used to control the power supply to SDRAM or external devices?

Turning on the power supply to both at the same time causes the external device to be started during a reset period, but this is OK as long as there are no problems caused by this timing.

The MPOWER signal is used to turn off the 1.5-V power supply for the CPU in Hibernate mode.
Any device (such as ROM) that does not require input of a power supply during Hibernate mode can be controlled by the MPOWER signal.

The SPOWER pin is used to turn off the SDRAM's power supply when supplying the power to the device for the first time.
When the power is supplied to the device, Hibernate mode is in effect until the POWERON signal becomes active after an RTC reset.
At this time, output to the data bus is at low level during this period.
This is because a pull-up resistor is required and the current consumption increases if the bus is in a high-impedance state.
However, since the status of the bus for SDRAM is undefined during the period from when the power is supplied to the SDRAM until the mode register is set, a conflict with the CPU's bus may occur during output.

The SPOWER signal is used to turn off the SDRAM power supply in order to avoid such conflicts.
However, most SDRAMs include a power-on reset function, which sets the device to high impedance immediately after the power supply.
In such cases, there is no need to use the SPOWER signal to control the power supply.

Regarding the VR4122 and its companion chip, it seems that the homepage lists the OS as up to Version 2.12.
What about Windows CE 3.0 support?

Windows CE 3.0 is supported.
If customers wish to develop Windows CE products featuring the VR4122, the version is Windows CE 3.0.

It seems that no LCD controller is provided in the companion chip.
What is the driver support status?

NEC Electronics has introduced third-party VR-compatible chipsets that feature an on-chip LCD controller.
For example, these third-part chipsets include XGA resolution products, and there are also chipsets with moving picture encoding/decoding as well as chipsets that enable video capture.

Can data be transferred from the external PCI bus master to the SDRAM attached to the CPU?

Yes, this is possible.

Regarding the PCI bus subset, is the PCI bus supported in its entirety?

No, PCI is not supported in its entirety for the following reasons.

Moreover, the following functional restrictions also apply.

During access to I/O devices, I want to input a wait signal to the VR4122.
Can the IORDY signal be input asynchronously to the VTClock inside the VR4122 ?

The IORDY signal can be input asynchronously.
The data sheet gives the min. spec of TCLR, but since IORDY is sampled when this spec has elapsed, to insert wait cycles in the IO bus cycle, wait for at least this time before making IORDY low.

Is there any problem if I insert LVC-type buffers between the VR4122 and ROM in order to connect 5V ROMs?

The specifications of the external bus interface of the VR4122 assume 3.3 Vdevices, and 5V devices cannot be connected directly because such devices exceed the absolute maximum ratings.
LVCMOS is a standard that satisfies the LVTTL standard interface requirements, and it is not related to the LVC Series.
When connecting 5V devices, insert buffers for level conversion between the VR4122 and the 5V memories.

Can the system clock or subsystem clock be input without connecting a crystal resonator?

Such clock input is possible if the system clock is input to the CLKX1 pin or the subsystem clock is input to the RTCX1 pin.
This is not recommended for ordinary use, however, since the PLL cannot be locked unless the system clock's frequency is 18.432 MHz.

Can the POWER signal be set as active at the same time as the RTCRST# signal is being released?

No, this is not possible.
As is shown in the RTC reset diagram in the User's Manual (Hardware), a period of at least 3RTC (= 92 us) is required between the rising edge of the RTCRST# signal and that of the POWER signal.

Do any hazards occur when accessing general-purpose registers other than the CP0 register?

No, no hazards occur when accessing any general-purpose registers.