VR10000,VR12000,VR12000A..( uPD30700, 30710, 30710A) (VR10000 was discontinued)

I think that the uPD30700RS-200 (Vr10000) can switch the CMOS/TTL and HSTL signal levels via the supply voltage of the VDDQSC and VDDQSYS pins, but during boundary scan testing, which level does the signal become, CMOS/TTL or HSTL ?

The JTAG pin is the CMOS/TTL level as the boundary scan control pin, but all the pins that are scanned during boundary scan testing (during execution) become the CMOS/TTL level.

Regarding the explanation in CHAPTER 10 JTAG INTERFACE OPERATION on p.203 of the VR10000 Series User's Manual (Version 4 March, 2001), there is a possibility that,

Is damage indeed caused to the core logic by applying a high level to both DCOK/SYSCLK and executing boundary scan?

Yes, this may cause fatal damage.

(Supplement) VR10000/12000 devices use a large number of dynamic circuits as part of their internal circuitry.
Therefore, when a suitable clock is not supplied, an excessive current will flow internally, damaging the device.
(This is the same as during normal operation.)

Regarding the case you inquire about, a suitable clock is not supplied internally, and such usage should be stopped.
(If DCOK is set to high, damage may be caused if a signal of 30MHz or higher is not supplied to the SYSCLK pin.)

What kind of damage can be caused?
(Destruction of core logic cells, or simply malfunction without physical damage?)

Physical damage may be caused.