V850 : A/D, D/A Conversion

• The A/D converter value is not correct.


• How are the A/D conversion results saved to registers?


• Conversion results are unstable (fluctuates to adjacent channel value) [V850/SF1, V850/SA, V850/SB, V850/SC]


• Clearing of CE bit of A/D [V853, V850E/MS, V850E/MA, etc.]


• Time to perform A/D conversion [V853]

V850 : Clock

• Switching time from subclock to main clock [V850]


• 50MHz clock input [V850E/MA1]


• Can the CERALOCK (resonator) be used in any mode other than PLL mode? [V850E/MS1]


• Is CLKOUT output possible during a reset period when in ROMless mode 0?


• Relationship between external clock and operating clock [V853]


• Can a 5-MHz input be used for the X1 input during PLL mode? [V853]


• Operation with 6.78MHz external clock [V853]


• Proper use of BUSCLK and CLKOUT [V850E/MA1]


• How much clock jitter and duty are allowed? [V850E/MA1]


• How can I dynamically change the clock in order to reduce power consumption? [V850E/MA1]


• Switching to the subsystem clock [V850/S]


• Clock settings in PLL mode [V850ES/SG2, SJ2]


• Relationship between reset and clock oscillation [All V850E]


• STOP mode during operation of subsystem clock [Common]

V850 : Serial Communication

• Basic operation of asynchronous communication (almost all contents common to all devices)


• Basic operation of 3-wire serial communication (almost all contents common to all devices)


• Synchronous serial communication in 16 bits.


• Usage of TO2/TO3 outputs when they are selected for the serial clock


• When using T02 or T03 as the clock output, can the T02 or T03 output pin be used as a normal port?


• No communication interrupt occurs after data output


• Cautions regarding power application when performing UART communication between two CPUs


• Prewriting 2 bytes of data at transmission start [V850E/MA1]


• Serial communication reception does not start.


• Use of software trigger bit at DMA startup [V850E/MA1]


• Stopping the operating clock when changing the communication settings


• Can data be received when TRMDn = 1 during synchronous serial communication?


• What is the timing for setting PM22 to "1" during serial communications? [V850E/MS1]


• Error recovery by maintaining UART input pin at a low level


• Sending unnecessary data during execution of initial settings


• Detection of break signal input from the UART serial interface.


• UART transmit/receive completion without using interrupts


• Timing of UART transmission interrupts [V850ES/Kx1, etc.]


• I cannot issue a start condition via the I2C bus [V850ES/Kx1]


• I would like to transmit data via 3-wire serial communications, but I cannot get any clock output for this. [V850ES/Kx1]


• How to use the clocked serial interface with automatic transmit/receive function [V850ES/Kx1]

V850 : Timer, Counter

• Output waveform when CRn0/1 is changed during processing [V850/S]


• Synchronization of multiple timers (simultaneous count start) [V850E]


• About settings for interval time


• Method for setting compare value when timers are connected in cascade fashion [V850/SB1]


• Upper limit of count clock of real-time pulse unit [V853]


• Use of real-time pulse unit as PWM output [V853]


• Sequence of settings in timer control register [V853]


• Using a 16-bit timer as an interval timer [V850ES/Kx1]


• Timer/counter function [V850ES/Kx1]


• Timer 2 operation [V850E/1A]


• Pulse width measurement with 8-bit timer [V850/SB]


• I cannot release STOP mode by using an INTP0n0/1 interrupt [V850/SV2]

V850 : Watchdog Timer

• Clearing watchdog timer during timer interrupt processing


• Operation following timeout of watchdog timer [All V850]


• Necessity to clear (RUN = 1) the watchdog timer prior to entering the STOP mode [All V850]


• Starting and stopping the watchdog timer by program


• Initialization with watchdog timer interrupts [V850/SA, V850/SB]

V850 : Interrupts

• Basic operations of interrupt servicing


• Interrupts doesn't work. (1) [All V850]


• Interrupts doesn't work. (2) [V850/S]


• Interrupts doesn't work. (3) [All V850]


• Interrupt request non-sample instruction


• Only one interrupt is output.


• Interrupt handler address


• Edge judgment method during interrupt [All V850]


• Can an interrupt be generated using the external interrupt pin level? [All V850]


• No interrupt request flag (P02IF1) is set. [V850E/MA1]


• Exception processing of illegal instruction code


• Initial interrupt during UART transmission [All V850]


• Multiple interrupts [All V850]


• Interrupt occurs during servicing of another interrupt [All V850]


• Interrupt handler address [All V850]


• Bus access and interrupts [All V850]


• Interrupts and manipulation of the interrupt control register [All V850]


• Initialization during interrupt service [All V850]


• Interrupts triggered by software [All V850]

V850 : Difference between PPG output and PWM output

• Difference between PPG output and PWM output [contents common to all devices]

V850 : DMA

• DMA usage (combination with real-time output function) [V850/Sxx]


• DMA usage (first data transmission in UART) [V850/Sxx]


• DMA transfer mode [V850/Sxx]


• Use of software trigger at DMA startup [V850E/MA1]


• Repeat of DMA startup [V850E]


• Settings for DMA restart [V850E/MA1]


• Pause of DMA [V850E/MS1]


• Misalignment by DMA [V850E/MA1, V850E/MA2, V850E/ME2]


• Endian ordering for DMA [V850E/MA1, V850E/MA2, V850E/ME2]


• Bus width for flyby transfers [V850E/MA, V850E/MS, V850E/ME]


• Wait during flyby transfer [V850E/MA, V850E/MS, V850E/ME]


• DMA transfer with I2C bus [V850/SB]

V850 : CAN

• CAN ; Message transmit/receive completion confirmation [V850/SF1]


• CAN ; Transmit/receive completion confirmation [V850/SF1]


• CAN ; Multiple internal register addresses [V850/SF1]


• CAN ; Settings in the various registers [V850/SF1]


• CAN ; Bus-off occurrence and detection [V850/SF1]


• CAN ; Receive message is missing. [V850/SF1]

V850 : IEBus

• IEBus of V850/SB2 [V850/SB2]


• IEBus ; Retransmission of the other communication party without reception. [V850/SB2]


• IEBus ; DR read upon overrun error [V850/SB2]


• IEBus ; Deletion of ISR after INTIE2 interrupt processing. [V850/SB2]


• IEBus ; Destination address of receive data during slave reception [V850/SB2]


• "Simplified version" of the IEBus controller

V850 : I2C Bus

• Overview of I2C bus

V850 : Execution Time

• Required clocks for V850 instructions


• Pipeline and instruction execution speed [V850E/IA1]


• States for bit manipulation instructions [V850/SA1]


• Execution speed [All V850]


• MIPS value calculation


• Programming area that allows the fastest processing


• Instruction execution in one clock through pipeline control

V850 : Programming

See also "Common Items FAQ : Cautions Regarding Bit Manipulation"

• Signed extension of MOVEA instruction


• What should be done (commonly) first after reset and start [common to V850]

V850 : Memory

• Access using the lower 8 bits of both even and odd addresses


• Cautions when performing byte access to external expansion memory


• Can the internal ROM be disabled and an external ROM used instead? [V850/SA1]


• Port 9 I/O mode with MM set for memory expansion [V850/SA1]


• SDRAM ; Access multiplex width setting [V850E/MA1]


• SDRAM ; Address signals to be connected to the bank signals [V850E/MA1]


• SDRAM ; Maximum SDRAM capacity [V850E/MA1]


• SDRAM ; AP settings during auto precharge [V850E/MA1]


• SDRAM ; Writing is not possible. [V850E/MA1]


• SDRAM ; Meanings of TWPRE and TWE [V850E/MA1]


• ROMless mode availability [V850E/MA1]


• Is the peripheral I/O register's address FFFFFxxxH? [V850E/MS1]


• Optimum type of external memory [V850E/MS1]


• A0 output during 16-bit access [V850E/MS1]


• DRAM ; Output for DRAM during access within the same page [V850E/MS1]


• DRAM ; Programmable wait [V850E/MS1]


• uPD703100 idle [V850E/MS1]


• Re-set of program wait? [V850E/MS1]


• Expansion of external memory up to 2MB [V853]


• Method to connect 8-bit and 16-bit external memory devices [V853]


• Address expansion [V853]


• Reason for not using A0 for external RAM connection [V853]


• Output signals when the internal area is accessed

V850 : ROMization

• Do files returned during the ROM ordering process use the same format as the files originally sent?

V850 : ROM Correction

• Details of ROM correction [V850/S]

V850 : Writing to Flash Memory

See also "Common Items FAQ : Flash Programming"

• Writing to flash memory


• CPU frequency when using the flash programmer [V853]


• Tools for writing to internal flash memory [V853]


• uPD70F3025A programming method changes

V850 : Power Supply

See also "78K : 78K Power Supply"

• Power consumption during a reset operation


• What mode reduces the power supply current most? (for lower power consumption)

V850 : Reset

• What is the timing for canceling a reset? Is it based on the rising edge or the level?


• Software reset


• Pulse width of reset signal


• Retention of RAM data after reset


• Clock stabilization time before reset release

V850 : Pins..DC Characteristics, Pin Handling

• Maximum value for pull-up resistors


• Schmitt trigger input threshold rating


• Handling of unused pins


• Pull-up of output pins to 5V [V850E/MA1]


• Can P00 to P07 be connected to VDD when they are not used? [V850E/MA1]


• Pull-up resistance values for unused pins and bus lines


• Application of high level to a port when there is no VDD power supply


• Processing of port/control alternate-function pins [V850E/MS1]

V850 : Other Peripheral Functions

• Simplification of external I/O connection method (address bus/data bus) [V850E/IA2]


• I/O connection address decode simplification [V850E/MS1]


• Can an undefined state be avoided by writing a value to a port with an undefined initial value before the undefined port is set to output mode?


• Which sampling edge of the WAIT signal is the correct one? [V850E/MA1]


• Can port input data be recognized even when the port has been set to control mode?


• When using the P111/A1/WAIT pin for wait function, can ports 3, 10, and 11 be used for address output? [V850/SB1]


• Please explain how the system wait control register (VSWC) is used. [All V850E and V850ES]

V850 : Product Differences

• Differences between no "A" suffix and "A" suffix for uPD70F3003A (V853)

V850 : Ratings

• uPD703107 output delay time


• CLKOUT synchronization and CLKOUT asynchronization standards (common to V850)

V850 : Other

See also "Common Items FAQ : PCB"

• Composite theoretical performance of uPD703015A (V850/SA1)


• Image of the internal peripheral I/O area


• Baking time

V850 : CA850

• Recovering stack frames


• Referencing the PSW in C language


• Initialization of external RAM


• Result of 0 division


• Absolute address specified in C language


• Bug (V2.30 and earlier) prevention option specifications (-Wo, -XTb)


• When unsigned short is shifted, it gets extended to the long type.


• Interrupt handler description


• Saving of the work registers (r10 through r14) for the interrupt handler


• Link directive description sequence


• romp850 ROMization tool


• Library creation


• Operating environment (multiprocessor)


• Volatile modifiers


• Optimization


• HEAP


• Translation limits


• Version information


• Error message (symbol_reset multiply defined)


• Error message (SCRx is not defined)


• Error message (xxx is too far from ...)


• Error message (No load segment exist for ...)


• Error message (W2231)


• Error message (W2525)


• AS850 symbol definition


• The message "Warning address is too long" is output.

V850 : SM850

• Simulation of communication functions using a simulator


• SM850 trace

V850 : RX850

• RX850 Pro interrupts [RX850 Pro]


• RX850 handler [RX850 Pro]


• Reduction of task stack area


• Start address of RX850 Pro


• Saving of ISP


• OS debugging method


• Usage of area acquired with get_blk


• DI processing in the OS


• The RX850 stops.


• PSW ID flag control


• Task priority


• System clock processing call


• Sample program


• Warning W2215 caused by "undeclared function call" option


• Distance between interrupt table and OS jump destination


• TCP/IP support for RTOS


• V850 TRON


• Differences between the RX850 and RX850 Pro


• RX850 Pro support

V850 : Debug..IE ID

See also "Common Items FAQ : Development Tool Parts"

• Operation is achieved with the in-circuit emulator, but not with the actual device.


• When there is an interrupt request on the in-circuit emulator, the STOP mode is not released. [V850/SA1]


• Difference between "-B" and "-C" for the IE interface board


• Use of the IE-703102-MC-EM1-A board


• Message "There is no response from the evaluation chip." from the IE-V850.


• Availability of on-chip debugging function (DCU) [V850E/MA1]


• External memory debugging [V850/SA1]


• Tools required to migrate from the V851 to the V850E/MS1


• Socket required for V850/SV1 (BGA) development.