Watchdog Timer

The watchdog timer is used to prevent CPU lockup.
To simplify the program, the watchdog timer is cleared during the periodical timer interrupt processing.
Is this OK?

We do not recommend that the watchdog timer be cleared during timer interrupt processing.
Because even if the main routine is locked up in this system, if a timer interrupt is acknowledged, the watchdog timer will be cleared and the system cannot detect a CPU lockup.

How does the CPU operate after the watchdog timer has timed out?

When a watchdog timer timeout occurs, a non-maskable interrupt (INTWTD) is generated.
If NMI processing is not in progress then, the interrupt is acknowledged, the interrupt with the exception code 0020H is generated, and the program branches to the handler address (00000020H).

For details of the processing that occurs at this time, refer to "5.2 Non-Maskable Interrupt" in Chapter 5 of the User's Manual (for V853, V850/SA1, V850/SB, etc.).
[Remark]
When a watchdog timer in a V850ES/Kx1, V850ES/SG2, V850ES/SJ2, V850ES/SA2, or V850ES/SA3 device experiences a timeout, you can specify either a reset or a non-maskable interrupt to occur.

The watchdog timer (WDT) stops in the STOP mode.
Why then is it necessary to clear (RUN = 1) the watchdog timer prior to entering the STOP mode?

Because the watchdog timer may overflow immediately before entering the STOP mode.
If it does, the system cannot enter the STOP mode.
To avoid this problem, WDT is cleared prior to entering the STOP mode.

Can the watchdog timer be started or stopped while a program is being executed?

The watchdog timer cannot be stopped by software once it is started.
Because the watchdog timer cannot be stopped by software, it can be used to monitor the program execution.
However, this operation differs for watchdog timer 2 in V850ES/Kx1 devices. (See Q2 below.)

This concerns about the V850ES/Kx1. After writing "ACH" to the watchdog timer enable register (WDTE), is it possible to stop the operation of watchdog timer 2 by setting the watchdog mode timer mode register 2 (WDTM2)?

Yes, that is possible.
The following description can be found in Note 1 under "12.2.1 Functions" in the User's Manual.

I would like to use processing of watchdog timer interrupts in V850 devices as a type of reset processing, but interrupts do not operate normally after control branches to reset processing.

This is because other interrupts cannot be acknowledged when processing is busy handling a watchdog timer interrupt.
This situation differs depending on whether the watchdog timer interrupts are being used as NMI or as ordinary (maskable) interrupts.

The corresponding bit in ISPR is set to 0 when the watchdog timer interrupts are used as ordinary interrupts. Perform the following processing in this event:

When the watchdog timer interrupts are used as NMI, the PSW.NP bit is set to "0" where no more interrupts can be acknowledged.
If a maskable interrupt is being serviced when an NMI occurs, the bit in ISPR register corresponding to that interrupt is set to "1."
Clear the NP bit first, and then perform the processing steps (1) to (3) shown above.

The following is a specific program sample.