Timer, Counter

Does the output waveform expand or contract halfway when the pulse ON width is changed with CRn0 at an arbitrary timing while the "PPG output function" of the 16-bit timer is operating?

When CRn1 is changed during processing, unintended waveforms may occur according to the overwrite timing.
To avoid this, processing such as using a match interrupt with CRn0 to overwrite CRn1 is required.

Is it OK to change the CRn0 value to change the interval without stopping the timer (PPG function)?

Yes, you can change it without stopping the timer.

Are there cautions that should be heeded when changing the interval?

If "Write to CRn0" and "Timing at which CRn0 and timer match" conflict, a match does not occur correctly.
Therefore, a write operation must not be performed close to the match timing.

Can a simultaneous count start be used to synchronize three timers?

No.
Each timer starts by setting TMCCE0 by program and this must be done independently.
Therefore, differences occur due to the command execution time and effects from the count clock cycle.

A 10ms interval timer operating with an external clock is gradually delayed.

Since the interval time is (n + 1), set (interval time -1) to the compare register.

In an 8-bit timer cascade connection (setting method in 7.4.5), suppose TM2 and TM3 are connected in cascade, should the compare value be set to CR20 and CR30 or should it be set to CR23 ?

Set it to 16-bit register CR23.

When the compare value is set to CR23, what becomes of INTTM2 and INTTM3 ?

When timers are connected in cascade, INTTM2 is generated when all 16 bits match.
Therefore, use INTTM2 as an interrupt when timers are connected in cascade.
In addition, the INTTM3 interrupt is generated when the higher 8 bits match, so mask INTTM3 when timers are connected in cascade.

How is the countable frequency determined when an external count clock is used as timer 1 input?

The external clock for timer 1 will be affected by the CPU clock frequency because of edge detection.
That is, to perform edge detection surely at both high and low levels, a width the equivalent of at least three cycles of CLKOUT is required.
The frequency is determined by this as well as other time required internally.
The standard specification is that at least 3T + 18ns is required (T is the cycle of CLKOUT).

Is a clock of the same frequency as the system clock countable?

No.
As explained above, a time of at least 3 CLKOUT + 18ns is required at both high level and low level.
For the specifications of the timer clock input, see the data sheet.

The V853 real-time pulse unit is used as PWM output.
To set the desired PWM period, I want to reset the counter as soon as the count value reaches the value set in the register.
It is necessary to input the reset signal at the TCLR pin to reset the register.

Therefore, is it OK to use the timer pulse output itself as the reset signal?

Basically, the method you mention is OK.
In addition, in a case like this, if ECLRn is set (clearance by external input is enabled) from the beginning, the timer does not start until TCLR1n is input.

Therefore, set CE1n first without setting ECLRn, start the timer, and then set ECLRn to enable external clearance.
Or set the timer output pin first as a port and as soon as a valid edge is output then change it to a timer output.
Here, TCLRn does not have to be delayed externally.

Is there a recommended (or required) sequence of settings in timer control register?

The target registers are:
  - Capture/compare registers (CC1n0 to CC1n3)
  - Timer output control register (TOC1n)
  - Timer control register (TMC1n)
  - Timer unit mode register (TUM1n)

First set the mode, then set the compare register.

  1. Set the count clock by TMC (leave CE bit as "0").
  2. Set TUM.
  3. Set TOC.
  4. Set CC.
  5. Set PMC.
  6. Set the CE bit of TMC to "1" to start the timer.

When using only CR0n0 for the capture/compare register while using a 16-bit timer as an interval timer, will there be any interrupts if CR0n1 is left as the default value?

The default setting is that the interrupt mask bit in the interrupt control register is set (to 1), so even if a match signal occurs, it will not trigger an interrupt.

The count register is cleared (to 0) when a match occurs with CR0n0.
Will this cleared status be compared with CR0n1 (default value: 0000)?

There will be a comparison with CR0n1.
Accordingly, when timer output or a CR0n1 match interrupt is used, timer output is inverted at 0000 or the CR0n1 match interrupt request flag is set.

The User's Manual contains the following description:
When output signals are switched to inverted output (toggled output) at any interval, can this switch occur without stopping the timer?

Yes, it can.
Normally, use this type of counter in the mode in which clear & start occurs on a match between the TM0n register and the CR0n0 register.
If necessary, overwrite the counter value to the next setting by a CRC0n0 match interrupt.
The caution point noted in the User's Manual can be avoided in this manner.

The User's Manual contains the following description:
How close is "close" in this case? How much difference is required for this value not to be "close"?

It is difficult to say specifically how close a value must be to be considered "close."
One way to consider a value as too close is if the value is exceeded by the counter's value before the next value is written.

In "9.3.4 Control registers - (8) CMSE120" in User's Manual, the description of the BFEEn bit concerning to the operations in the capture register mode and when CVSEn0 is used as a buffer says:

When the CPU reads the main register during the INTCC24 interrupt that occurred when sub-channel 4 was captured by an external signal (INTP24 pin), what does the CPU read from that register?

The value captured from TM20 is read.

When a similar capture occurs and the CPU reads the sub-register during the INTCC24 interrupt, does it read TM20's capture values then as well?

Yes, that is correct.
However, there are no more captures after the sub-register is read, so the main register must be read.

I understand that when CVSEn0 is not used as a buffer (BFEEn bit = 0), the next capture will not occur unless the main register is read.
Why is this?

A built-in control circuit is provided to secure synchronization between two registers for cascade connection, and when reading the sub-register and the main register in this order, the values of the both registers are the values at the same timing.
This type of control works for non-cascade connections as well.

I would like to connect an 8-bit timer via a cascade connection and use DMA to read the timer's values and measure the pulse width.
Is this possible?

It is possible if you use an external pulse input to INTP6 or INTP0 and specify this as a DMA start trigger.

In this case, will the data differ from the data captured with the 16-bit timer?

The data will not change as long as no other higher-priority DMA is operating.
However, when using INTP6, a large difference may occur if the noise elimination clock's frequency is low.
Change the noise elimination clock's frequency to fxx.

When such a difference occurs, is it always for the same reason and is the number of clock cycles constant?

It is considered as only natural that the timing for reading count values is shifted by the effects of higher-priority DMA.
As for noise elimination, the external input signal is not synchronous with the noise elimination clock, so the sampling interval will also fluctuate. In either case, the effects are not constant.

I have set external interrupts INTP040, 041, 050, and 051 for releasing STOP mode, but these interrupts do not occur so STOP mode cannot be released.
During normal operation, external interrupts INTP040, 041, 050, and 051 occur normally.

External interrupt signals that are used as capture signals for the timer cannot operate if the timer is stopped.
Since the timer's clock is stopped (which stops the timer) while in STOP mode, from that point onward it is not possible to release STOP mode using these external interrupts.